An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors

Bouajila, Abdelmajid; Zeppenfeld, Johannes; Stechele, Walter; Herkersdorf, Andreas

doi:10.1109/ddecs.2011.5783084

Cited by 10 publications

(6 citation statements)

References 19 publications

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“…Bouajila et al [20] has proposed an spatial redundancy based fault mitigation technique for RISC processors in general, while the actual implementation was merely carried out for LEON3 processors. The underlying objective of the proposed approach is to detect and correct any faults occurring in the pipeline registers of the processor.…”

Section: A Spatial Redundancy Based Solutionsmentioning

confidence: 99%

“…4, where register replicas are referred to as shadow registers. The modified version of the pipeline works as follows: whenever the utilised ECC modules supervising pipeline registers detect an error, the pipeline is frozen at the current clock cycle and then the corrupted data is corrected in the second clock cycle deploying the complex mechanism explain in Section III-A of [20]. Therefore, any error will be detected and corrected with a fixed penalty of two clock cycles.…”

Section: A Spatial Redundancy Based Solutionsmentioning

confidence: 99%

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Survey of Soft Error Mitigation Techniques Applied to LEON3 Soft Processors on SRAM-Based FPGAs

et al. 2020

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Soft-core processors implemented in SRAM-based FPGAs are an attractive option for applications to be employed in radiation environments due to their flexibility, relatively-low application development costs, and reconfigurability features enabling them to adapt to the evolving mission needs. Despite the advantages soft-core processors possess, they are seldom used in critical applications because they are more sensitive to radiation than their hard-core counterparts. For instance, both the logic and signal routing circuitry of a soft-core processor as well as its user memory are susceptible to radiation-induced faults. Therefore, soft-core processors must be appropriately hardened against ionizing-radiation to become a feasible design choice for harsh environments and thus to reap all their benefits. This survey henceforth discusses various techniques to protect the configuration and user memories of an LEON3 soft processor, which is one of the most widely used soft-core processors in radiation environments, as reported in the stateof-the-art literature, with the objective of facilitating the choice of right fault-mitigation solution for any given soft-core processor.

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Section: A Spatial Redundancy Based Solutionsmentioning

confidence: 99%

Section: A Spatial Redundancy Based Solutionsmentioning

confidence: 99%

Survey of Soft Error Mitigation Techniques Applied to LEON3 Soft Processors on SRAM-Based FPGAs

et al. 2020

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“…Possible solutions are the extension of registers with ECC [3] or the use of Dual Interlocked CEll flip flops (DICE) [4]. These protection schemes induce higher chip costs, thus it is not practical to protect all registers.…”

Section: A Fault Injection Into Registersmentioning

confidence: 99%

“…In hardware, error correcting codes (ECC) and additional registers with a delayed clock have been shown to reliably protect a microprocessor [3]. On a lower level, DICE-based flip-flops with an SET pulse discriminator are also able to tolerate SEUs and SETs [4].…”

Section: Introductionmentioning

confidence: 99%

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Identification of critical variables using an FPGA-based fault injection framework

Riefert

Müller

Sauer

et al. 2013

2013 IEEE 31st VLSI Test Symposium (VTS)

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Abstract-The shrinking nanometer technologies of modern microprocessors and the aggressive supply voltage down-scaling drastically increase the risk of soft errors. In order to cope with this risk efficiently, selective hardware and software protection schemes are applied. In this paper, we propose an FPGA-based fault injection framework which is able to identify the most critical registers of an entire microprocessor. Furthermore, our framework identifies critical variables in the source code of an arbitrary application running in its native environment. We verify the feasibility and relevance of our approach by implementing a lightweight and efficient error correction mechanism protecting only the most critical parts of the system. Experimental results with state estimation applications demonstrate a significantly reduced number of critical calculation errors caused by faults injected into the processor.

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Matching Detection and Correction Schemes for Soft Error Handling in Sequential Logic

Koser

Miller

Stechele

2015

2015 Euromicro Conference on Digital System Design

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An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors

Cited by 10 publications

References 19 publications

Survey of Soft Error Mitigation Techniques Applied to LEON3 Soft Processors on SRAM-Based FPGAs

Survey of Soft Error Mitigation Techniques Applied to LEON3 Soft Processors on SRAM-Based FPGAs

Identification of critical variables using an FPGA-based fault injection framework

Matching Detection and Correction Schemes for Soft Error Handling in Sequential Logic

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