1987
DOI: 10.1016/0743-7315(87)90005-0
|View full text |Cite
|
Sign up to set email alerts
|

An architecture and an interconnection scheme for time-sliced buses

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

1995
1995
1995
1995

Publication Types

Select...
2
1

Relationship

0
3

Authors

Journals

citations
Cited by 3 publications
(1 citation statement)
references
References 16 publications
0
1
0
Order By: Relevance
“…Therefore, SPIDER is designed to bound low-level communication delays. Access to interfaces in SPIDER is governed by fair, demand-slotted arbitration [21], and all of the interfaces are designed to avoid blocking. This allows SPIDER to guarantee that all channels can access the memory within certain bounds.…”
Section: Predictabilitymentioning
confidence: 99%
“…Therefore, SPIDER is designed to bound low-level communication delays. Access to interfaces in SPIDER is governed by fair, demand-slotted arbitration [21], and all of the interfaces are designed to avoid blocking. This allows SPIDER to guarantee that all channels can access the memory within certain bounds.…”
Section: Predictabilitymentioning
confidence: 99%