An architecture for asynchronous FPGAs

Wong, C.G.; Martin, Alain J.; Thomas, P.

doi:10.1109/fpt.2003.1275745

Cited by 32 publications

(16 citation statements)

References 10 publications

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“…There have been a number of asynchronous FPGAs developed over the past 10+ years [20][21][22][23][24][25][26][27][28]11]. MONTAGE [20] was developed to support both synchronous and asynchronous circuits.…”

Section: Previous Workmentioning

confidence: 99%

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Design of a logic element for implementing an asynchronous FPGA

Smith

2007

Proceedings of the 2007 ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays

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A reconfigurable logic element (LE) is developed for use in constructing a NULL Convention Logic (NCL) FPGA. It can be configured as any of the 27 fundamental NCL gates, including resettable and inverting variations, and can utilize embedded registration for gates with three or fewer inputs. The developed LE is compared with a previous NCL LE, showing that the one developed herein yields a more area efficient NCL circuit implementation. The NCL FPGA logic element is simulated at the transistor level using the 1.8V, 180nm TSMC CMOS process.

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Section: Previous Workmentioning

confidence: 99%

“…Two other asynchronous FPGAs [25][26][27] are both based on the precharge half-buffer (PCHB) logic family to implement quasi delay-insensitive circuits. Both use data-driven decomposition (DDD) [30] to convert a high-level circuit description into PCHB circuits.…”

Section: Previous Workmentioning

confidence: 99%

Design of a logic element for implementing an asynchronous FPGA

Smith

2007

Proceedings of the 2007 ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays

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“…Other architectures were based on "porting" a clocked FPGA architecture, and the result was relatively low throughput [6], [15], [8]. More recently, there has been work that is similar in spirit to the design described here, where an asynchronous FPGA architecture based on programmable pipeline stages was proposed [24]. There has also been a some work on prototyping asynchronous logic using commercially available synchronous FPGAs (e.g.…”

Section: Introductionmentioning

confidence: 95%

Reconfigurable Asynchronous Logic

Manohar

2006

IEEE Custom Integrated Circuits Conference 2006

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Abstract-Challenges in mapping asynchronous logic to a flexible substrate include developing a balance between circuitlevel flexibility, mapping complexity, and logic overhead. We have developed a reconfigurable dataflow architecture that addresses these challenges, and have also created the necessary synthesis flow required to map designs to the architecture. The architecture exploits some of the unique features of asynchronous logic, and attains a performance that significantly exceeds previous asynchronous FPGAs.

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“…Despite these issues, there have been attempts to implement asynchronous designs on synchronous FPGAs [100]; however, such approaches have been found to incur significant area and performance penalties [193]. Therefore, to enable more efficient asynchronous implementations, new FPGA architectures that incorporate asynchronous elements directly have been proposed [95,110,158,193,194,215]. We will briefly review these architectures and then summarize the architectural issues facing asynchronous FPGA designs.…”

Section: Asynchronous Fpgasmentioning

confidence: 99%

“…The current trend appears to be toward developing software that hides the asynchronous design details [63,215]. As was noted in the discussion of coarse-grained architectures, well-developed CAD tools will be necessary to enable the rigorous experimental methodologies, as described in Section 4.2, that are used to evaluate current FPGA architectures.…”

Section: Asynchronous Architecture Issuesmentioning

confidence: 99%

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

331

109

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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An architecture for asynchronous FPGAs

Cited by 32 publications

References 10 publications

Design of a logic element for implementing an asynchronous FPGA

Design of a logic element for implementing an asynchronous FPGA

Reconfigurable Asynchronous Logic

FPGA Architecture: Survey and Challenges

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