An architecture for tolerating processor failures in shared-memory multiprocessors

Abstract

This paper focuses on the problem of fault tolerance in shared memory multiprocessors, and describes an architecture designed for transparently tolerating processor failures. The Recoverable Shared Memory (RSM) is the novel component of this architecture, providing a hardware supported backward error recovery mechanism which minimizes the propagation of recovery when a processor fails. The RSM permits a shared memory multiprocessor to be constructed using standard caches and cache coherence protocols, and does not require any changes to be made to applications software. The performance of the recovery scheme supported by the RSM is evaluated and compared with other schemes that have been proposed for fault tolerant shared memory multiprocessors. The performance study has been conducted by simulation using address traces collected from real parallel applications.

A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures

“…While a line is in backup state its data is considered invalid and will be used only if required for recovery. Hence, the cache will not be able to read from that line 2 . Also, when a line enters in a backup state the lost data timeout will start and will stop once the backup state is abandoned.…”

“…Once C1 receives it, it transitions to a normal modified state. A cache line in a backup state will be used for recov- 2 It is possible for a cache to receive valid data and a token before abandoning a backup state, only if the data message was not lost. In that case, it will be able to read from that line and the line will be transitioned to an intermediate backup state until the ownership acknowledgement is received.…”

SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery

“…5. We only present the results for the static web server, but these results are qualitatively the same for all of our other workloads.…”

“…Logging due to transferring cache ownership, however, does not incur additional bandwidth, since the cache line must be read anyway. In Figure 6, for the static web server workload 5 , we plot this frequency as a function of the checkpoint interval. Both axes use log scales.…”

“…The Sequoia system [7] uses caches to hold state between checkpoints, and flushes dirty cache blocks to memory at every checkpoint. Banâtre et al [5] describe a Recoverable Shared Memory module that requires a shadow copy of the entire memory and a mechanism for maintaining the interprocessor dependence graph. checkpointing has also been used, but at radically different engineering costs.…”