An architecture of high-performance frequency and phase synthesis

Mair, Hugh; Xiu, Liming

doi:10.1109/4.845187

Cited by 103 publications

(56 citation statements)

References 7 publications

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“…Figure 11 shows another example where FREQ = 10. Table 2 compares this work to the other works and also shows significant jitter improvement compared to the FA-FS [5] that adopts the TAF approach.…”

Section: Measurement Resultsmentioning

confidence: 72%

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An instant-switching ∆–Σ fractional-N frequency synthesizer with adjustable duty cycles

Huang

Gui

Fan

et al. 2011

Analog Integr Circ Sig Process

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A Phase-Locked Loop (PLL)-based frequency synthesizer (FS) with adjustable duty cycle is presented. By employing digital processing circuitry and the D-R fractional-N technique, the FS is capable of generating arbitrary frequencies in a wide frequency range, and capable of adjusting the clock duty cycles. In addition, the switching between different frequencies is instant except when a very fine frequency resolution is required. The adjustable duty cycle and instant switching are desired features in applications such as time-interleaved Analog-to-DigitalConverters (ADCs), switched-capacitor circuits, and DC-DC converters. The design was fabricated using a 0.13 lm CMOS process. This paper gives the theories, analysis, implementation, and measurement results of this FS.

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Section: Measurement Resultsmentioning

confidence: 72%

“…The Flying-Adder (FA) FS is capable of achieving wide frequency range and instant switching at low cost [5][6][7]. In order to meet the frequency resolution requirement, the FA synthesizer adopts the Time-Average-Frequency (TAF) concept [8].…”

Section: Introductionmentioning

confidence: 99%

An instant-switching ∆–Σ fractional-N frequency synthesizer with adjustable duty cycles

Huang

Gui

Fan

et al. 2011

Analog Integr Circ Sig Process

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show abstract

“…This however introduces the challenging task of generating single-bit digital signals of desirable sinewavelike spectrum using only the reference clock [6], [9] [2]. Unless the generated frequency is an integer fraction of the clock, their output waveforms are irregular with high deterministic jitter and spectra full of strong frequency spurs, usually close to the carrier.…”

Section: Introductionmentioning

confidence: 99%

All Digital Frequency Synthesis based on Pulse Direct Digital Synthesizer with spurs free output and improved noise floor

Sotiriadis

2014

2014 IEEE International Frequency Control Symposium (FCS)

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This work presents Direct-Digital Frequency Synthesis architectures based on the classical Pulse-Direct Digital Synthesizer and using two quantization paths with opposite dithers or multi-path quantization with independent dithers to achieve spurs-free output with improved dynamic range. The proposed architectures are studied mathematically and the theory is supported by MATLAB simulation results.

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“…To generate the final output waveform, CLK2, the FA-DFC selects the appropriate VCO output signal at the time needed to trigger the flip-flop [2]. It is these VCO output waveforms that are input to the FA-DFC that make up the final output combined with PATHA and PATHB working together.…”

Section: A Flying-adder Digital-to-frequency Convertermentioning

confidence: 99%

A digital-to-frequency converter using redundant signed binary addition

Chen¹,

Thornton²,

Gui³

2009

2009 52nd IEEE International Midwest Symposium on Circuits and Systems

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Abstract-Redundant signed binary addition (RSBA) has been used to create high performance arithmetic circuits. This paper presents an accumulator-based digital-tofrequency (DFC) converter employing redundant signed binary addition (RSBA). RSBA is advantageous in that no carry propagation occurs resulting in constant delay regardless of operand word size. Utilizing RSBA in the proposed DFC resolves the performance bottleneck in the DFC's conventional implementation and achieves extremely high frequency resolution. In addition, a new RSBA-based 8:1 Multiplexer is introduced for a complete RSBA implementation of the DFC. Experimental results show an increase of more than 3.5 times in the speed of the accumulator compared to the conventional implementation regardless of bit size of the adder.

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An architecture of high-performance frequency and phase synthesis

Cited by 103 publications

References 7 publications

An instant-switching ∆–Σ fractional-N frequency synthesizer with adjustable duty cycles

An instant-switching ∆–Σ fractional-N frequency synthesizer with adjustable duty cycles

All Digital Frequency Synthesis based on Pulse Direct Digital Synthesizer with spurs free output and improved noise floor

A digital-to-frequency converter using redundant signed binary addition

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