An Architecture to Enable Life Cycle Testing in CMPs

Abstract

CMOS wear-out mechanisms such as time dependent breakdown of gate dielectrics (TDDB), hot carrier injection (HCI), negative bias temperature instability (NBTI), electromigration (EM), and stress induced voiding (SIV) are well documented in the literature. Often the onset of wear-out is gradual, with initial manifestation as delay defects that result in timing errors. This motivates the need for online testing. The combined effect of dynamic reconfiguration such as voltage and frequency scaling (DVFS) and signal integrity issues coupled with aging related wear-outs complicate a priori selection of test vectors, further favoring online testing. Traditional online test techniques such as Double and Triple Modular Redundancy (DMR and TMR) pose severe area and power overheads. In this paper we propose an architecture to assist online testing in a Chip Multiprocessor (CMP) based on execution path recording. Since in practice, core utilization in CMPs is low, we can use the idle time of cores opportunistically to run test threads that mimic functional threads. The initiation, termination and comparison of test results is performed by a dedicated, simple and functionally limited small core that we call the Sentry Core (SC). The sentry core is hidden from the OS and has the ability to monitor and interrupt the general-purpose cores. Upon interrupt, the general-purpose core can send data to the sentry core. To detect errors, the SC initializes the general-purpose cores and collects signatures from hardware monitors (that compact execution traces) and compares them against duplicate test threads, obviating any need for cycle by cycle comparison. Major benefits of the proposed solution include: (1) online testing with minimal area overhead, (2) scalability, and (3) testability throughout the life cycle of a CMP. Experimental results show that the proposed scheme is capable of detecting 87% of the faults injected into the processor at an area overhead of less than 3% of the target CMP.

Stochastic testing of processing cores in a many-core architecture

“…They have added various hardware components to apply a test to the processing cores and check their responses. Several works [18][19][20] have used natural core-level redundancy available in a CMP and used processing power of a processing core to test correct operation of another processing core. [21,22] have incorporated BIST (Built-In Self-Test) components into the CMP architecture and have provided a mechanism that periodically triggers the BIST circuitry to test various components of a CMP.…”