An Area- and Energy-Efficient FIFO Design Using Error-Reduced Data Compression and Near-Threshold Operation for Image/Video Applications

Zeinolabedin, Seyed Mohammad Ali; Zhou, Jun; Liu, Xin; Kim, Tony Tae-Hyoung

doi:10.1109/tvlsi.2014.2369052

Cited by 6 publications

(9 citation statements)

References 24 publications

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“…We implement and test the datapath unit of size 64‐row × 64‐bit using SRAM 8T‐Cells, which is a common FIFO size in many chips 1–4,7,8 . Additionally, two control units, one with synchronous and the other with asynchronous circuitry, are implemented and integrated with datapath unit for testing purposes.…”

Section: Results and Comparison Analysismentioning

confidence: 99%

“…An additionally advantage factor is that the datapath processes write and read operations without any latencies, which is usually implemented as brute‐force, cascaded DFFs in other designs 4–20 to synchronize the incoming data with the internal clock. Thus, the datapath exploits high overall performance and processes data on every cycle (i.e., every two nonoverlapping signals process new data).…”

Section: Results and Comparison Analysismentioning

confidence: 99%

“…Since both implementations have advantages and disadvantages, the greatest design consideration is to determine the most appropriate implementation based on system and/or application requirements. Typically, synchronous FIFOs are used in microprocessors to manage handshaking communications between on‐chip components, such as queue management, 1 reorder buffers, 2 arithmetic logic units (ALUs), 3 etc., and more recently, in Artificial Intelligence (AI), 4,5 graphics cards, 6,7 etc. These synchronous implementations leverage the existing clock generator resources within the chip (e.g., delay‐locked loop (DLL) and phase‐locked loop (PLL)) and the same on‐chip component and fabrication technology.…”

Section: Introductionmentioning

confidence: 99%

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Reconfigurable FIFO memory circuit for synchronous and asynchronous communication

Abdel‐hafeez

Gordon‐Ross

2021

Circuit Theory & Apps

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We present a new FIFO (first‐in first‐out) architecture for both synchronous and asynchronous communication for high‐speed and low‐power operation. Our FIFO design is reconfigurable and scalable using a separate datapath with an 8T‐Cell SRAM and control circuits, which enables specialization for different application requirements. The datapath uses a two‐phase clock system of nonoverlapping signals such that one signal increments the address pointer, while the other signal activates the memory decoder for data reading and writing. This structure halves the critical path delay and simplifies the timing operations between the memory decoder and address pointer while maintaining robustness against process‐voltage‐temperature (PVT) variations. Our design uses two alternative control circuits to manage separate synchronous and asynchronous operations by generating nonoverlapping control signals that drive the datapath circuit. The empty‐full flag circuitry records only the state of the address pointers' rollover independent of the memory size, and, thus, improves scalability and reconfigurability. Compared to prior works, our design is 5X faster with a 2.3X lower power consumption and has a throughput of 1 Giga‐Word/s. For a 64‐bit word size with a free latency cycle. Additionally, our design functions clocklessly with the synthesizable structure for asynchronous communication that leverages Internet of Things (IoT) and Networks on Chip (NoCs) applications.

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Section: Results and Comparison Analysismentioning

confidence: 99%

Section: Results and Comparison Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Reconfigurable FIFO memory circuit for synchronous and asynchronous communication

Abdel‐hafeez

Gordon‐Ross

2021

Circuit Theory & Apps

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“…Therefore, there are various approaches towards image compression where hardware approach has been considered. Study focusing over the energy efficiency as well as constraint area of the ciruit design connecting with the concept of image compression has been discussed by Zeinolabedin et al [29]. Kim et al [30] has used encoding-based approach for carrying the compression operation where the preliminary encoding computes the bitstream length while the secondary encoder is responsible for generation of streams of the data packets over VLSI architecture.…”

Section: Introductionmentioning

confidence: 99%

Novel hybrid framework for image compression for supportive hardware design of boosting compression

Premachand¹,

Eranna²

2021

IJECE

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Performing the image compression over the resource constrained hardware is quite a challenging task. Although, there has been various approaches being carried out towards image compression considering the hardware aspect of it, but still there are problems associated with the memory acceleration associated with the entire operation that downgrade the performance of the hardware device. Therefore, the proposed approach presents a cost effective image compression mechanism which offers lossless compression using a unique combination of the non-linear filtering, segmentation, contour detection, followed by the optimization. The compression mechanism adapts analytical approach for significant image compression. The execution of the compression mechanism yields faster response time, reduced mean square error, improved signal quality and significant compression ratio performance.

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“…FAERDC along with a proposed extension method and a near-threshold operation have been applied in LP (including GP) as a sample popular hardware accelerator. The LP has been fabricated in 180 nm CMOS technology and its functionality is verified at 0.5 V. We have published these works in [23], [24], [25], [26].…”

Section: Summary Of Thesis Contributionsmentioning

confidence: 99%

Ultra-low power signal processor for biomedical applications

Zeinolabedin¹

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An Area- and Energy-Efficient FIFO Design Using Error-Reduced Data Compression and Near-Threshold Operation for Image/Video Applications

Cited by 6 publications

References 24 publications

Reconfigurable FIFO memory circuit for synchronous and asynchronous communication

Reconfigurable FIFO memory circuit for synchronous and asynchronous communication

Novel hybrid framework for image compression for supportive hardware design of boosting compression

Ultra-low power signal processor for biomedical applications

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