An Area-Efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets

Section: Challenges For Traditional Redundancy Based Hardened Latchesmentioning

confidence: 99%

“…At present, lots of redundancy based latches are proposed to mitigate the SEU [2,3,4]. There latches are effective to eliminate the SEU when only one node collects charge.…”

Section: Introductionmentioning

confidence: 99%

Multiple nodes upset tolerance DICE latch based on on-state transistor

Zhang

Qin

2014

“…Many approaches have been designed to mitigate SEU in flip-flops, such as the increasing critical charge technique, spatial redundancy techniques [1,2,3]. The redundancy-based hardened latches are very effective to mitigate SEU when only one node collects charge.…”

Section: Introductionmentioning

confidence: 99%

Circuit and layout combination technique to enhance multiple nodes upset tolerance in latches

Zeng

2015

In this paper, we propose a novel hardened latch to mitigate the SEU. The combination of the circuit structure and layout placement is adopted to enhance the multiple nodes upset tolerance. This latch consists of a normal D latch and a typical DICE latch. Different from the TMR latch, this latch can mitigate the charge collection on two transistors. HSPICE simulation results present that there only exit four sensitive transistor pairs in this latch. Compared to the typical DICE and DMR latch, the sensitive transistor pairs are largely reduced. And by adjusting the layout placement, these sensitive transistor pairs are separated from each other as much as possible. From the view of the layout, it is almost impossible for charge collection on the sensitive transistor pairs in our proposed latch.

“…It can weaken the hardening performance of many radiation hardened techniques. Generally, the charge sharing effect will invalid the redundancy based hardened flip-flops, such as DICE [4], DMR [5] and TMR [6]. Also, it can increase the probability of single-event multiple transient (SEMT) which can increase the soft error rate (SER).…”

Section: Introductionmentioning

confidence: 99%

DICE-based test structure to measure the strength of charge sharing effect

Yun

Liang

2015

With the technology scaling, the charge sharing effect is becoming more prominent. Using the property of DICE latch, we present a DICEbased test structure to measure the strength of charge sharing effect. Threedimensional TCAD simulations are done to simulate the DICE property. And a test chip is fabricated by the commercial 65 nm bulk CMOS process to verify our proposed test structure. Heavy-ion experiment results indicate that this test structure is efficient to obtain the strength of charge sharing effect.