An area efficient and high throughput multi-rate quasi-cyclic LDPC decoder for IEEE 802.11n applications

Roberts, Michaelraj Kingston; Ramesh, J.

doi:10.1016/j.mejo.2014.07.003

Cited by 9 publications

(4 citation statements)

References 27 publications

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“…It should be noted that since the decoding algorithm is not modified, the BER performance graph is similar to a traditional LDPC decoder using offset min‐sum algorithm. For instance, decoding the half‐rate code shows similar BER performance as in 18,19 . Therefore, without deteriorating the BER performance, the minimum throughput of the decoder as a result of decoding shorter code lengths can be improved by factors of two and four depending on code size.…”

Section: Decoder Implementation Resultsmentioning

confidence: 98%

“…For instance, decoding the half-rate code shows similar BER performance as in. 18,19 Therefore, without deteriorating the BER performance, the minimum throughput of the decoder as a result of decoding shorter code lengths can be improved by factors of two and four depending on code size.…”

Section: Decoder Implementation Resultsmentioning

confidence: 99%

“…The decoder in 15 uses a non-reconfigurable barrel shifter that only supports Z = 96 and half-rate WiMAX (1152, 2304). Similarly, the barrel shifter in 18 only supports Z = 81. The resulted decoder supports one out of three code lengths used in IEEE 802.11n.…”

Section: Decoder Flexibility Comparisonmentioning

confidence: 99%

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A high‐throughput multimode low‐density parity‐check decoder for 5G New Radio

Pourjabar

Choi

2021

Circuit Theory & Apps

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This paper presents a partially parallel low-density parity-check (LDPC) decoder for the 5G New Radio (NR) standard. The design is using a multiblock parallel architecture with a flooding schedule. The decoder can support any code rates and code lengths up to the lifting size Z max = 96. To compensate for the dropped throughput associated with the smaller Z values, the design can double and quadruple its parallelism when lifting sizes Z ≤ 48 and Z ≤ 24 are selected, respectively. Therefore, the decoder can process up to eight frames and restore the throughput to the maximum. To facilitate the design's architecture, a new variable node for decoding the extended parity bits existing in the lower code rates is proposed. The FPGA implementation of the decoder results in a throughput of 2.1 Gbps decoding the 11/12 code rate. Additionally, the synthesized decoder using the 28-nm TSMC technology achieves a maximum clock frequency of 526 MHz and a throughput of 13.46 Gbps. The core decoder occupies 1.03 mm 2 , and the power consumption is 229 mW.

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Section: Decoder Implementation Resultsmentioning

confidence: 98%

Section: Decoder Implementation Resultsmentioning

confidence: 99%

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A high‐throughput multimode low‐density parity‐check decoder for 5G New Radio

Pourjabar

Choi

2021

Circuit Theory & Apps

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“…A reliable soft information field is obtained through the iterative propagation of the message. Many scholars have worked to achieve the best trade-offs between latency, resource overhead, throughput, and power consumption [9,10]. The post-processing phase removes the possible SBs and only retains the valid information field DBs needed by the medium access control (MAC).…”

Section: Decoding Processmentioning

confidence: 99%

High-Performance QC-LDPC Code Co-Processing Approach and VLSI Architecture for Wi-Fi 6

Zhou

2023

Electronics

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The QC-LDPC code, with its excellent error correction performance and hardware friendliness, has been identified as one of the channel encoding schemes by Wi-Fi 6. Shorting, puncturing, or repeating operations are needed to ensure that user data can be sent with integer symbols and complete rate matching. Due to the uncertainty of the user data size, the modulation’s selectivity, and the difference in the number of spatial streams, the receiver must deal with more than 106 situations. At the same time, other computationally intensive tasks occupy the time slot budget of the receiver. Typical are demodulation and decoding. Hence, the receiver needs to quickly reverse the demodulated data process. This paper first proposes a co-processing method and VLSI architecture compatible with all code lengths, code rates, and processing parameters. The co-processor separates field and block splicing, simplifying the control logic. There is no throughput rate bottleneck, and the maximum delay is less than 1 us.

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Certain investigations on recent advances in the design of decoding algorithms using low‐density parity‐check codes and its applications

Roberts¹,

Kumari

Anguraj³

2021

Int J Communication

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Summary Information theory coding is an impressive and most celebrated field of research that has spawned numerous extremely important solutions to the intractable problems of secure data communications. Recent advancements in error control coding methods have seen a huge surge in using low‐density parity‐check (LDPC) code‐based decoding algorithms to solve imperative issues related to reliable data transmission and reception. Till date, extensive research efforts have been consistently being made on LDPC codes which focus on algorithm‐driven and hardware‐realization‐based approaches. The main intension of this research work is to provide an extensive systematic elucidation on the recent advancements in LDPC decoding algorithms. In addition, a thorough performance evaluation and analysis of several outstanding LDPC decoding techniques is presented. Finally, conclusions are drawn by summarizing the important research findings, interesting open problems, current challenges and broader perspectives for future directions of research.

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An area efficient and high throughput multi-rate quasi-cyclic LDPC decoder for IEEE 802.11n applications

Cited by 9 publications

References 27 publications

A high‐throughput multimode low‐density parity‐check decoder for 5G New Radio

A high‐throughput multimode low‐density parity‐check decoder for 5G New Radio

High-Performance QC-LDPC Code Co-Processing Approach and VLSI Architecture for Wi-Fi 6

Certain investigations on recent advances in the design of decoding algorithms using low‐density parity‐check codes and its applications

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