An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications

Ganjikunta, Ganesh Kumar; Sahoo, Subhendu Kumar

doi:10.1016/j.vlsi.2016.12.002

Cited by 16 publications

(9 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…So, the SDF design style preferred to design the FFT structure. It's easy to style and utilizes low memory elements [13]. For the multi-band OFDM ultra-wideband system, the SDF design style based FFT processor proposed by Nuo Li and co-worker in [14].…”

Section: A Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Design of an Area-Efficient Various N-point Support radix-2/22 FFT using Modified Butterfly Units

Anguraj¹,

Krishnan²,

Natesan³

2019

IJRTE

View full text Add to dashboard Cite

Fast Fourier Transform (FFT) acts as an element in the high-speed signal processing application, which involves the following subsequent operations, namely complex addition, complex subtraction and complex multiplication. Due to the complex multiplication operation, the FFT structures lead to more hardware demand. Hence, this work introduces an area-efficient various N-point support radix-2 and radix-22 FFT structure by using proposed modified butterfly units and radix-2/22 butterfly unit. The proposed modified butterfly units are used to reduce the number of complex multipliers effectively. For this reason, it is using for certain conditions in FFT design instead of existing radix-2/22 butterfly unit. Further, the proposed design supported to perform various size of FFT in a single architecture without increasing the extra element demand. Moreover, the proposed FFT structure designed and implemented using a Xilinx Virtex-6 Field-Programmable Gate Array (FPGA) device (6vcx75tff484-2) and Cadence tool with 45nm CMOS technology. The implementation results demonstrate that the proposed N-point (N=16, 32 and 64) DIF-FFT design attains the less hardware complexity when compared with existing multi-mode FFT design. Then the proposed area-efficient 16-point, 32-point and 64-point radix-2 FFT architectures reduce the total area by 20.99%, 11% and 4.9% respectively. As well, the proposed area-efficient 16-point, 32-point and 64-point radix-22 FFT architectures reduce the total area by 32%, 19% and 11% respectively.

show abstract

Section: A Related Workmentioning

confidence: 99%

“…In this section, two kinds of FFT algorithms, namely radix-2 and radix-2 2 DIF-FFT algorithms are discussed briefly. In general, the computational expression of Discrete Fourier Transform (DFT) [13] can be expressed as…”

Section: Design Consideration Of Radix-2/2 2 Dif-fftmentioning

confidence: 99%

Design of an Area-Efficient Various N-point Support radix-2/22 FFT using Modified Butterfly Units

Anguraj¹,

Krishnan²,

Natesan³

2019

IJRTE

View full text Add to dashboard Cite

show abstract

“…However, the hardware cost because of the multipliers used is high with a fixed length. Therefore, these architectures [16][17][18] are not suitable for variablelength FFTs.…”

Section: Introductionmentioning

confidence: 99%

“…CSD complex constant multiplier for CCM1 and CCCM CSD complex constant multiplier for CCM2[18] 128 configurable constant multiplier block diagram eight terms ('0', '1', '−1', '101', '10-1', '-101', '−10-1', and '100-1') in CSD form are used to construct the common subexpression block. The sharing block consisting of shifters, adders, and two's complement is shown inFig.…”

mentioning

confidence: 99%

Area and power‐efficient variable‐length fast Fourier transform for MR‐OFDM physical layer of IEEE 802.15.4‐g

Ganjikunta¹,

Sahoo²

2020

IET Computers & Digital Techniques

View full text Add to dashboard Cite

The authors present a novel 16/32/64/128-point single-path delay feedback pipeline fast Fourier transform (FFT) architecture targeting the multi-rate and multi-regional orthogonal frequency division multiplexing (MR-OFDM) physical layer of IEEE 802.15.4-g. The proposed FFT architecture employs a mixed-radix algorithm to significantly reduce the number of complex multipliers. It utilises a configurable complex constant multiplier structure instead of a fixed constant multiplier to efficiently conduct W 32 , W 64 , and W 128 twiddle factor multiplication. A hardware-sharing mechanism has also been formulated to reduce the memory space requirements of the proposed 16/32/64/128-point FFT computation scheme. The proposed design is implemented in Xilinx Virtex-5 and Altera's field-programmable gate array devices. For the computation of 128-point FFT, the proposed mixed-radix FFT architecture significantly reduces the hardware cost in comparison with existing FFT architecture. The proposed FFT architecture is also implemented by adopting the 90 nm complementary metal-oxide-semiconductor technology with a supply voltage of 1 V. Post-synthesis results reveal that the design is efficient in terms of gate count and power consumption, compared to earlier reported designs. The proposed variable-length FFT architecture gate count is 22.3K and consumes 3.832 mW, while the word-length is 12-bits and can be efficiently useful for the IEEE 802.15.4-g standard.

show abstract

“…Ever since its introduction, the computational advantages of the FFT have made it an essential algorithm with widespread applications in science and engineering, such as communication, signal processing, image processing, bio-robotics, and intelligent maintenance [1,2,4,[7][8][9][10]. The high-speed requirements of smart maintenance systems, such as fault diagnosis in rotary machines using the spectral analysis of AE signals, necessitate a high-performance FFT processor.…”

Section: Introductionmentioning

confidence: 99%

A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis

et al. 2018

View full text Add to dashboard Cite

Abstract:The fast Fourier transform (FFT) is the most prevalent algorithm for the spectral analysis of acoustic emission signals acquired at ultra-high sampling rates to monitor the condition of rotary machines. The complexity and cost of the associated hardware limit the use of FFT in real-time applications. In this paper, an efficient hardware architecture for FFT implementation is proposed based on the radix-2 decimation in frequency algorithm (R2DIF) and a feedback pipelined technique (FB) that allows effective sharing of storage between the input and output data at each stage of the FFT process via shift registers. The proposed design uses an optimal hybrid rotation scheme by combining the modified coordinate rotation digital computer (m-CORDIC) algorithm and a binary encoding technique based on canonical signed digit (CSD) for replacing the complex multipliers in FFT. The m-CORDIC algorithm, with an adaptive iterative monitoring process, improves the convergence of computation, whereas the CSD algorithm optimizes the multiplication of constants using a simple shift-add method. Therefore, the proposed design does not require the large memory typically entailed by existing designs to carry out twiddle factor multiplication in large-point FFT implementations, thereby reducing its area on the chip. Moreover, the proposed pipelined FFT processor uses only distributed logic resources and does not require expensive dedicated functional blocks. Experimental results show that the proposed design outperforms existing state-of-the-art approaches in speed by about 49% and in resource utilization by around 51%, while delivering the same accuracy and utilizing less chip area.

show abstract

An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications

Cited by 16 publications

References 14 publications

Design of an Area-Efficient Various N-point Support radix-2/22 FFT using Modified Butterfly Units

Design of an Area-Efficient Various N-point Support radix-2/22 FFT using Modified Butterfly Units

Area and power‐efficient variable‐length fast Fourier transform for MR‐OFDM physical layer of IEEE 802.15.4‐g

A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis

Contact Info

Product

Resources

About