An Area Efficient Diode and On Transistor Interchangeable Power Gating Scheme with Trim Options for Low Power SRAMs

Goel, Anubha; Evans, Donald; Stephani, R.; Rai, Dharmendra; Chary, Veerabadra; Sathisha, N

doi:10.1109/vlsid.2012.50

Cited by 2 publications

(2 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The shutdown mode design is as shown in Figure 13(b), which has modified control logic transistor. The modified design can be operated in both light sleep and shutdown modes [92].…”

Section: Diode and On Transistor Interchangeable Techniquementioning

confidence: 99%

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

Bikki¹,

Karuppanan²

2017

View full text Add to dashboard Cite

Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.

show abstract

“…The shutdown mode design is as shown in Figure 13(b), which has modified control logic transistor. The modified design can be operated in both light sleep and shutdown modes [92].…”

Section: Diode and On Transistor Interchangeable Techniquementioning

confidence: 99%

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

Bikki¹,

Karuppanan²

2017

View full text Add to dashboard Cite

show abstract

“…The virtual gnd (VSSC) raise limits become even more stringent when NBTI/PBTI factors are taken into account [14]. Thirdly, most of these schemes except [12, 15, 16] do not provide an option to cut off the memory leakage in the shutdown (SD) mode, where SRAM cell contents need not be retained. Programmable bias transistors shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Area efficient diode and on transistor inter‐changeable power gating scheme with trim options for SRAM design in nano‐complementary metal oxide semiconductor technology

Goel¹,

Sharma²,

Gupta³

2014

IET Circuits, Devices & Systems

Self Cite

View full text Add to dashboard Cite

Reducing the leakage power in embedded static random access memory (SRAM) memories is critical for low-power applications. Raising the source voltage of SRAM cells through diode transistor in standby mode reduces the leakage currents effectively. However, in order to preserve the state of the cell in standby mode, the source voltage cannot be raised beyond a certain level. To achieve that, the size of the required diode transistor becomes larger, as the supply voltage shrinks in the nanocomplementary metal oxide semiconductor (CMOS) technologies. In this work, an area efficient power gating technique with capability of post-silicon trimming of the voltage across SRAM cell is presented. Proposed scheme provides many options to trim the SRAM source voltage (ranging from 50 to 150 mV in steps of 25 mV approximately.) with 3% area overhead when applied to complete SRAM bank. The scheme has been illustrated with a 16 kb SRAM macro at 28 nm CMOS technology at 0.85 V supply voltage. Sector-based power gating is presented which enables leakage savings while memory is in the active mode. The area overhead of the presented scheme is 8% when applied to SRAM bank array split into sectors.

show abstract

An Area Efficient Diode and On Transistor Interchangeable Power Gating Scheme with Trim Options for Low Power SRAMs

Cited by 2 publications

References 7 publications

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

Area efficient diode and on transistor inter‐changeable power gating scheme with trim options for SRAM design in nano‐complementary metal oxide semiconductor technology

Contact Info

Product

Resources

About