2018
DOI: 10.1166/sl.2018.3985
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An Area-Efficient FPGA Implementation of Network-on-Chip (NoC) Router Architecture for Optimized Multicore-SoC Communication

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Cited by 6 publications
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“…The synchronization of redundant resources is the basis of switching, and the computer realizes the synchronization of three computers through flight control cycle synchronization [9] . The schematic diagram of aircraft computer single flight control cycle synchronization design requirements is shown in the figure 2.…”
Section: 1time Synchronization Policymentioning
confidence: 99%
“…The synchronization of redundant resources is the basis of switching, and the computer realizes the synchronization of three computers through flight control cycle synchronization [9] . The schematic diagram of aircraft computer single flight control cycle synchronization design requirements is shown in the figure 2.…”
Section: 1time Synchronization Policymentioning
confidence: 99%