An area-efficient Radix 28 FFT algorithm for DVB-T2 receivers

Turrillas, M.; Cortés, A.; Vélez, Igone; Sevillano, Juan F.; Irizar, A.

doi:10.1016/j.mejo.2013.10.016

Cited by 4 publications

(3 citation statements)

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“…7 for the FFT module adopting CORDIC units. Apart from the optimized solutions we proposed, the feasible schemes offered by [24] and [25] serve as references here, where and are jointly optimized under the constraint if the FFT size . We relax the constraint to , making the selection of more flexible.…”

Section: B Analysis Of Simulation Resultsmentioning

confidence: 99%

“…Numerous of state-of-the-art pipelined processors, whether adopting the feed forward approach [15]- [18] or the feedback scheme [19]- [25], give preference to the radixcomputing strategy. Nevertheless, the existing fixed-point analysis of radix-scheme reveals insufficiency to cope with the issues in practical applications, which has motivated the first part of research in this paper.…”

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confidence: 99%

“…For radixarchitectures equipped with integer multipliers, [15]- [23] provide a rough estimate of memory expenditure without considering the cost of twiddle factors storage. This work has been extended in [3], [24], [25] by incorporating the memories used for storing twiddle factors into the overall cost. Based on these existing studies, we further generalize the issue to the extended radix-FFT scenario, where the multi-path delay commutator (MDC) [15] and single path delay feedback (SDF) [19] serve as the representative to cover the topics related to the feed-forward and feed-back radix-pipelined processor.…”

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confidence: 99%

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Fixed-Point Analysis and Parameter Optimization of the Radix-<formula formulatype="inline"><tex Notation="TeX">$2^{k}$</tex> </formula> Pipelined FFT Processor

Jian

Xiong

Zhang

et al. 2015

IEEE Trans. Signal Process.

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The radix-algorithm plays a crucial role in the pipelined implementation of fast Fourier transform (FFT). This paper presents a fixed-point analysis and hardware evaluation of radix-FFT under the framework of the single-path delay feedback (SDF) and multi-path delay commutator (MDC) pipelined structure. The investigation is carried out with variable operating word-lengths to ensure the generality. Furthermore, the main streams to fulfill FFT coefficients weighting, namely, the approach using complex multipliers and the one adopting memoryless CORDIC units, are both considered in the analysis. Based on these derivations, a joint optimization of radixalgorithm and operating word-length is discussed to achieve a reasonable trade-off between computational accuracy and hardware expenditure. Simulations and experiments indicates that the derived SQNR is reliable to unfold the quantization effects of fixed-point radix-FFT. In addition, the proposed joint optimization strategy is capable of providing better solutions to implement the radix-FFT processor efficiently.Index Terms-Fast Fourier transform (FFT), fixed-point accuracy, multi-path delay commutator (MDC), radix-algorithm, single-path delay feedback (SDF).

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Section: B Analysis Of Simulation Resultsmentioning

confidence: 99%

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confidence: 99%