2006 2nd IEEE/ASME International Conference on Mechatronics and Embedded Systems and Applications 2006
DOI: 10.1109/mesa.2006.297007
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An Area-Efficient Reed-Solomon Decoder for HDTV Channel Demodulation

Abstract: In this paper, an area-efficient pipelined very large scale integration (VLSI) architecture is proposed for Reed-Solomon (RS) decoding. The proposed architecture is exploited based on the features of vector operations of the decoding algorithm. By pipelining and folding, the proposed architecture can improve the reuse rate of the main computation unit, reduce the hardware complexity and delete the redundant circuits. Synthesized by the Cadence Ambit TM tool using the TSMC 0.25 µm standard cell library, the imp… Show more

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