An Area-Optimized and Power-Efficient CBC-PRESENT and HMAC-PHOTON

Ngo, Chi Trung; Eshraghian, Jason K.; Hong, Jong-Phil

doi:10.3390/electronics11152380

Cited by 3 publications

(1 citation statement)

References 34 publications

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“…However, this connectivity necessitates enhanced security to address potential vulnerabilities such as unauthorized access, data breaches, and cyberattacks [1]. Existing security measures face various drawbacks, including resource constraints on IoT devices, cryptographic complexity, and evolving adversarial tactics [2,3]. Alternative security paradigms suitable for the IoT's unique attributes must be explored to address these challenges.…”

Section: Introductionmentioning

confidence: 99%

A Reconfigurable SRAM CRP PUF with High Reliability and Randomness

Pham,

Ngo,

Nam

et al. 2024

Electronics

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This paper presents a novel reconfigurable SRAM CRP PUF that can achieve high reliability and randomness. In conventional reconfigurable SRAM CRP PUFs, imprecise timing control can produce a biased response output, which is typically attributed to mismatches in the connection of input control signals to the two inverter arrays in the layout floorplan. We propose a timing control scheme along with the addition of an adjunct NMOS transistor to address this issue. This eliminates the connection mismatches for the challenge and word-line inputs to the two inverter arrays. Furthermore, we employ symmetric layout techniques to achieve the randomness of response output. The symmetric arrangement of the two inverter arrays maximizes the inherent random output characteristics derived from process variation. The pre-charge input signal is symmetrically connected to each array to prevent delay mismatches. A 16 × 9-bit reconfigurable PUF array is fabricated by using a 180 nm CMOS process, with a PUF cell area of 1.2 × 104 F2/bit. The experimental results demonstrate an inter Hamming distance of 0.4949 across 40 chips and an intra Hamming distance of 0.0167 for a single chip in 5000 trials. The measured worst bit error rate (BER) is 4.86% at the nominal point (1.8 V, 25 °C). The proposed prototype exhibits good reliability and randomness, as well as a small silicon area when compared to the conventional SRAM CRP PUFs.

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Section: Introductionmentioning

confidence: 99%

A Reconfigurable SRAM CRP PUF with High Reliability and Randomness

Pham,

Ngo,

Nam

et al. 2024

Electronics

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Implementation of a Hash-based Secure Core for Integrity and Authentication of Data in Space Applications on Space-grade FPGAs

Crocetti,

Falaschi,

Saponara

et al. 2023

2023 IEEE 2nd Industrial Electronics Society Annual on-Line Conference (ONCON)

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A Lightweight and High Yield Complementary Metal-Oxide Semiconductor True Random Number Generator with Lightweight Photon Post-Processing

Ngo,

Ko,

Choi

et al. 2024

Sensors

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This paper introduces a novel TRNG architecture that employs a wave converter to generate random outputs from the jitter noise in a customized ring oscillator (RO). Using a current-starved inverter, the proposed RO offers the option of operating three different oscillation frequencies from a single oscillator. To assess its performance, the core TRNG proposed in this work was designed with multiple samples, employing various transistor sizes for 28 nm CMOS processes. The measurements show that only a small number of measured TRNG samples passed the randomness NIST SP 800-22 tests, which is a common problem, not only with the proposed TRNG but also with other TRNG structures. To solve this issue, a lightweight post-processing algorithm using the Photon hash function was newly applied to the proposed TRNGs topology. The lightweight Photon hash function-based post-processing was implemented with the proposed TRNG topology in a 28 nm CMOS process. The design occupies 16,498 µm2, with a throughput of 0.0142 Mbps and power consumption of 31.12 mW. Measurements showed significant improvement, with a 50% increase in chips passing the NIST SP 800-22 tests. Compared with the conventional DRBG post-processing method, the proposed lightweight Photon post-processing reduces area occupation by five times and power consumption by 65%.

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An Area-Optimized and Power-Efficient CBC-PRESENT and HMAC-PHOTON

Cited by 3 publications

References 34 publications

A Reconfigurable SRAM CRP PUF with High Reliability and Randomness

A Reconfigurable SRAM CRP PUF with High Reliability and Randomness

Implementation of a Hash-based Secure Core for Integrity and Authentication of Data in Space Applications on Space-grade FPGAs

A Lightweight and High Yield Complementary Metal-Oxide Semiconductor True Random Number Generator with Lightweight Photon Post-Processing

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