2013 IEEE International Reliability Physics Symposium (IRPS) 2013
DOI: 10.1109/irps.2013.6532005
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An array-based circuit for characterizing latent Plasma-Induced Damage

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Cited by 6 publications
(2 citation statements)
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“…V th and gate leakage current are increased by PID because defects are generated in a gate oxide. [20][21][22][23][24] V th increases when defects trap carriers. It is called the atomistic trap-based BTI model, [5][6][7][8][9][10] as shown in Fig.…”
Section: Degradation Caused By Plasma-induced Damagementioning
confidence: 99%
“…V th and gate leakage current are increased by PID because defects are generated in a gate oxide. [20][21][22][23][24] V th increases when defects trap carriers. It is called the atomistic trap-based BTI model, [5][6][7][8][9][10] as shown in Fig.…”
Section: Degradation Caused By Plasma-induced Damagementioning
confidence: 99%
“…In previous studies, differences between SiO 2 and HK gate dielectrics 25) in terms of antenna shape (e.g., square and comb) 26) and thickness 27) were evaluated. BTI caused by PID was also evaluated in the study of Choi et al 28) Our research focused on PID depending on the type of antenna layer, particularly the second to fifth metal layers (M2-M5) in SSDM 2017.…”
Section: Introductionmentioning
confidence: 99%