An assessment of RTN-induced threshold voltage jitter

Zhang, Chenglong; Manut, Azrif; Gao, Rui; Mehedi, Mehzabeen; Ji, Zhigang; Weidong, Zhang; Marsland, John

doi:10.1109/asicon47005.2019.8983559

Cited by 2 publications

(4 citation statements)

References 17 publications

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“…The discriminator threshold (Vth) is connected to the inverting input and set by an internal 10-bit resistor string DAC [13]. Since the preamplifier's baseline varies with temperature, bias setting, and irradiation, the DAC output ranges from 0.6 to 1 V with an LSB (Least significant bit) of 0.4 mV.…”

Section: Discriminator and Dacmentioning

confidence: 99%

Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection

Sun¹,

Gong²,

Zhang³

et al. 2021

J. Inst.

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We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS technology, reads out a 16× 16 pixel matrix of the Low-Gain Avalanche Detector (LGAD). The jitter contribution from ETROC is required to be below 40 ps to achieve the 50 ps overall time resolution per hit. The analog readout circuits in ETROC consist of the preamplifier and the discriminator. The preamplifier handles the LGAD charge signal with the most probable value of around 15 fC. The discriminator generates the digital pulse, which provides the Time-Of-Arrival (TOA, leading edge) and Time-Over-Threshold (TOT, pulse width) information. The prototype of ETROC (ETROC0) that implements a single channel of analog readout circuits has been evaluated with charge injection. The jitter of the analog readout circuits, measured from the discriminator's leading edge, is better than 16 ps for a charge larger than 15 fC with the sensor capacitance. The time walk resulting from different pulse heights can be corrected using the TOT measurement. The time resolution distribution has a standard deviation of 29 ps after the time-walk correction from the charge injection. At room temperature, the preamplifier's power consumption is measured to be 0.74 mW and 1.53 mW per pixel in the low- and high-power mode, respectively. The measured power consumption of the discriminator is 0.84 mW per pixel. With the ASIC alone or the LGAD sensor, The characterization performances fulfill the ETL's challenging requirements.

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Section: Discriminator and Dacmentioning

confidence: 99%

Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection

Sun¹,

Gong²,

Zhang³

et al. 2021

J. Inst.

View full text Add to dashboard Cite

show abstract

“…The equivalent baseline for the ASIC alone is about 30 DAC LSB higher than that on the LGAD sensor, translating to a shift of 12 mV. Note that the step size of the DAC is 0.4 mV [6]. Provided that the default feedback resistance is 5.5 kΩ, an equivalent LGAD leakage current of 2.2 μA contributes to the preamplifier baseline.…”

Section: Fpga Verificationmentioning

confidence: 99%

“…As an ideal model for discriminator pulse generator is used in the simulation, the results do not include the non-linearity of the DAC mainly introduced by the mismatch. In ETROC, the DAC non-linearity does not introduce calibration error as the monotonicity of the DAC is guaranteed by design [6]. The gate-level simulation with SEEs injection is conducted as well, and the majority voting and the error auto-correction are verified.…”

Section: Implementation and Verificationmentioning

confidence: 99%

“…One ETROC has a 16 × 16 pixel matrix and global circuits at the bottom of the pixel matrix, as shown in figure 1. Each pixel channel in ETROC consists of a preamplifier, a discriminator, a time-to-digital converter (TDC) [5], an in-pixel readout block, a local I 2 C-based slow control block, and a digital-to-analog converter (DAC) [6] for discriminator threshold setting.…”

Section: Introductionmentioning

confidence: 99%

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In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip

Sun¹,

Gong²,

Edwards³

et al. 2021

J. Inst.

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We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC) needs to be calibrated regularly to mitigate the circuit baseline change. Traditional methods need a lot of communication through a slow control system hence are time-consuming. This paper describes an in-pixel automatic scheme with improvements in operating time and usability. In this scheme, a sample-accumulation circuit is used to measure the average discriminator output. A binary successive approximation and linear combination scan are applied to find the equivalent baseline. The actual calibration procedure has been first implemented in FPGA firmware and tested with the ETROC front-end prototype chip (ETROC0). The calibration circuit has been implemented with Triple Modular Redundancy (TMR) and verified with Single Event Effects (SEEs) simulation. A complete calibration process lasts 35 ms with a 40 MHz clock. In the worst case, the dynamic and static power consumption are estimated to be 300 μW and 10.4 μW, respectively. The circuit design, implemented in a 65 CMOS technology, will be integrated into ETROC2, the next iteration of the ETROC with a 16 × 16 pixel matrix.

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An assessment of RTN-induced threshold voltage jitter

Cited by 2 publications

References 17 publications

Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection

Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection

In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip

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