An Assessment of Sample Preparation Challenges in 3D Stacked Integrated Circuit Devices for Post-Silicon Verification and Validation

Padro, Noah; Patel, Yash; Scholl, Jon; Kelley, John; Waite, Adam R.; Sale, Matt; Kimura, Adam

doi:10.1109/paine58317.2023.10317984

2023 IEEE Physical Assurance and Inspection of Electronics (PAINE) 2023

DOI: 10.1109/paine58317.2023.10317984

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An Assessment of Sample Preparation Challenges in 3D Stacked Integrated Circuit Devices for Post-Silicon Verification and Validation

Noah Padro,

Yash Patel,

Jon Scholl

et al.

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Cited by 2 publications

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Scholl,

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2024 IEEE Physical Assurance and Inspection of Electronics (PAINE)

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Applying a Trusted Microelectronics Post-Silicon Verification & Validation Workflow to Legacy Integrated Circuit Design Recovery

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Padro,

Patel

et al. 2024

2024 IEEE Physical Assurance and Inspection of Electronics (PAINE)

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et al. 2024

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An Assessment of Sample Preparation Challenges in 3D Stacked Integrated Circuit Devices for Post-Silicon Verification and Validation

Cited by 2 publications

References 18 publications

Applying a Trusted Microelectronics Post-Silicon Verification & Validation Workflow to Legacy Integrated Circuit Design Recovery

Applying a Trusted Microelectronics Post-Silicon Verification & Validation Workflow to Legacy Integrated Circuit Design Recovery

Third-Party IP Verification and Validation for Post-Silicon Recovered Designs

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