An asymmetrical sensing scheme for 1T1C FRAM to increase the sense margin

Abstract

A novel asymmetrical current-based sensing scheme for 1T1C FRAM is proposed, in which the two input transistors are not the same size and a feedback NMOS is added at the reference side of the sense amplifier. Compared with the conventional symmetrical scheme in Ref. [8], the proposed scheme increases the sense margin of the readout current by 53.9% and decreases the sensing power consumption by 14.1%, at the cost of an additional 7.89% area of the sensing scheme. An experimental FRAM prototype utilizing the proposed asymmetrical scheme is implemented in a 0.35 m three metal process, in which the function of the prototype is verified.

Reference voltage generation scheme enhancing speed and reliability for 1T1C‐type FRAM

“…Introduction: Ferroelectric random access memory (FRAM) is a promising non-volatile memory, among which 1T1C (one transistor and one capacitor)-type FRAM has more competitiveness for embedded and standalone data storage applications with technologies of integrated circuits scaled down [1][2][3][4]. To generate a reference signal for data-sensing is a challenge for the 1T1C-type FRAM design [5,6]. The reference scheme of two full-sized reference capacitors per two columns/bitlines (BLs) [7] (2C/2BL) has been widely utilised due to its generation of an accurate reference voltage.…”