An Asymptotic Performance/Energy Analysis and Optimization of Multi-core Architectures

Lee, Jeong-Gun; Jung, Eun-Gu; Shin, Wook

doi:10.1007/978-3-540-92295-7_13

Cited by 5 publications

(6 citation statements)

References 3 publications

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“…Previous studies on multicore performance modeling [Chakraborty 2008;Cho and Melhem 2008;Chung et al 2010;Hill and Marty 2008;Lee et al 2009;Loh 2008;Woo and Lee 2008] use Pollack's rule [Pollack 1999] to denote the trade-off between area and performance. Furthermore, these studies consider the power consumption of a core to be directly proportional to its area.…”

Section: Decoupling Power/performance Trade-off From Area/performancementioning

confidence: 99%

“…Previous studies have also analyzed these features in various combinations, but not together [Chakraborty 2008;Cho and Melhem 2008;Chung et al 2010;Hempstead et al 2009;Hill and Marty 2008;Lee et al 2009;Loh 2008;Venkatesh et al 2010;Woo and Lee 2008]. This study builds and combines three models to project performance and the fraction of "dark silicon" (transistor integration underutilization) on fixed-size and fixed-power chips as listed here.…”

Section: Introductionmentioning

confidence: 95%

“…Hill and Marty [2008] extend Amdahl's Law to model multicore speedup with symmetric, asymmetric, and dynamic topologies and conclude dynamic multicores are superior. Several extensions to the Hill and Marty model have been developed for modeling "uncore" components (e.g., interconnection network and last level cache), [Loh 2008], computing core configuration optimal for energy [Cho and Melhem 2008;Lee et al 2009], and leakage power [Woo and Lee 2008]. All these model uses area as the primary constraint and model single-core area/performance tradeoff using Pollack's rule (Performance ∝ √ Area [Pollack 1999]) without considering technology trends.…”

Section: Model Limitationsmentioning

confidence: 99%

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Power Limitations and Dark Silicon Challenge the Future of Multicore

Esmaeilzadeh

Blem

Amant

et al. 2012

ACM Trans. Comput. Syst.

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Since 2004, processor designers have increased core counts to exploit Moore's Law scaling, rather than focusing on single-core performance. The failure of Dennard scaling, to which the shift to multicore parts is partially a response, may soon limit multicore scaling just as single-core scaling has been curtailed. This paper models multicore scaling limits by combining device scaling, single-core scaling, and multicore scaling to measure the speedup potential for a set of parallel workloads for the next five technology generations. For device scaling, we use both the ITRS projections and a set of more conservative device scaling parameters. To model single-core scaling, we combine measurements from over 150 processors to derive Pareto-optimal frontiers for area/performance and power/performance. Finally, to model multicore scaling, we build a detailed performance model of upper-bound performance and lower-bound core power. The multicore designs we study include single-threaded CPU-like and massively threaded GPU-like multicore chip organizations with symmetric, asymmetric, dynamic, and composed topologies. The study shows that regardless of chip organization and topology, multicore scaling is power limited to a degree not widely appreciated by the computing community. Even at 22 nm (just one year from now), 21% of a fixed-size chip must be powered off, and at 8 nm, this number grows to more than 50%. Through 2024, only 7.9× average speedup is possible across commonly used parallel workloads for the topologies we study, leaving a nearly 24-fold gap from a target of doubled performance per generation.

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Section: Decoupling Power/performance Trade-off From Area/performancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 95%

Section: Model Limitationsmentioning

confidence: 99%

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Power Limitations and Dark Silicon Challenge the Future of Multicore

Esmaeilzadeh

Blem

Amant

et al. 2012

ACM Trans. Comput. Syst.

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show abstract

“…Previous studies on multicore performance modeling [8,9,10,15,20,22,28] use Pollack's rule [6] to denote the tradeoff between transistor count and performance. Furthermore, these studies consider the power consumption of a core to be directly proportional to its transistor count.…”

Section: Decoupling Area and Power Constraintsmentioning

confidence: 99%

“…We consider technology scaling projections, single-core design scaling, multicore design choices, actual application behavior, and microarchitectural features together. Previous studies have also analyzed these features in various combinations, but not all together [8,9,10,14,15,20,22,27,28]. This study builds and combines three models to project performance and fraction of "dark silicon" on fixed-size and fixed-power chips as listed below:…”

Section: Introductionmentioning

confidence: 99%

Dark silicon and the end of multicore scaling

Esmaeilzadeh

Blem

Amant

et al. 2011

SIGARCH Comput. Archit. News

310

215

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Since 2005, processor designers have increased core counts to exploit Moore's Law scaling, rather than focusing on single-core performance. The failure of Dennard scaling, to which the shift to multicore parts is partially a response, may soon limit multicore scaling just as single-core scaling has been curtailed. This paper models multicore scaling limits by combining device scaling, single-core scaling, and multicore scaling to measure the speedup potential for a set of parallel workloads for the next five technology generations. For device scaling, we use both the ITRS projections and a set of more conservative device scaling parameters. To model singlecore scaling, we combine measurements from over 150 processors to derive Pareto-optimal frontiers for area/performance and power/performance. Finally, to model multicore scaling, we build a detailed performance model of upper-bound performance and lowerbound core power. The multicore designs we study include singlethreaded CPU-like and massively threaded GPU-like multicore chip organizations with symmetric, asymmetric, dynamic, and composed topologies. The study shows that regardless of chip organization and topology, multicore scaling is power limited to a degree not widely appreciated by the computing community. Even at 22 nm (just one year from now), 21% of a fixed-size chip must be powered off, and at 8 nm, this number grows to more than 50%. Through 2024, only 7.9× average speedup is possible across commonly used parallel workloads, leaving a nearly 24-fold gap from a target of doubled performance per generation.

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A framework for energy-efficient optimization on multi-cores

Zhu

et al. 2016

2016 Seventh International Green and Sustainable Computing Conference (IGSC)

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An Asymptotic Performance/Energy Analysis and Optimization of Multi-core Architectures

Cited by 5 publications

References 3 publications

Power Limitations and Dark Silicon Challenge the Future of Multicore

Power Limitations and Dark Silicon Challenge the Future of Multicore

Dark silicon and the end of multicore scaling

A framework for energy-efficient optimization on multi-cores

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