An asynchronous and reconfigurable CNN accelerator

Chen, Weijia; Wang, Dengjie; Chen, Hong; Wei, Shaojun; He, Anping; Wang, Zhihua

doi:10.1109/edssc.2018.8487115

Cited by 5 publications

(3 citation statements)

References 3 publications

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“…In these power and hardware resource-limited circumstances, to improve performance and reduce power consumption, many researchers have proposed CNN accelerators at various design levels including system level, application level, architecture level, and transistor level [7], [8], [9]. Recent studies have proposed a flexible CNN accelerator design for FPGA implementation at the system level and a flexible FPGA accelerator for various CNN architectures from lightweight CNN to large-scale CNN [11], [12], [13], [14], [15], [16].…”

Section: Convolutional Neural Network(cnn)-based Object Detection App...mentioning

confidence: 99%

A Reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

Kim

Choi

2023

IEEE Access

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In limited-resource edge computing circumstances such as on mobile devices, IoT devices, and electric vehicles, the energy-efficient optimized convolutional neural network (CNN) accelerator implemented on mobile Field Programmable Gate Array (FPGA) is becoming more attractive due to its high accuracy and scalability. In recent days, mobile FPGAs such as the Xilinx PYNQ-Z1/Z2 and Ultra96, definitely have the advantage of scalability and flexibility for the implementation of deep learning algorithm-based object detection applications. It is also suitable for battery-powered systems, especially for drones and electric vehicles, to achieve energy efficiency in terms of power consumption and size aspect. However, it has the low and limited performance to achieve real-time processing. In this article, optimizing the accelerator design flow in the register-transfer level (RTL) will be introduced to achieve fast programming speed by applying low-power techniques on FPGA accelerator implementation. In general, most accelerator optimization techniques are conducted on the system level on the FPGA. In this article, we propose the reconfigurable accelerator design for a CNN-based object detection system on the register-transfer level on mobile FPGA. Furthermore, we present RTL optimization design techniques that will be applied such as various types of clock gating techniques to eliminate residual signals and to deactivate the unnecessarily active block. Based on the analysis of the CNN-based object detection architecture, we analyze and classify the common computing operation components from the Convolutional Neuron Network, such as multipliers and adders. We implement a multiplier/adder unit to a universal computing unit and modularize it to be suitable for a hierarchical structure of RTL code. The proposed system design was tested with Resnet-20 which has 23 layers and it was trained with the dataset, CIFAR-10 which provides a test set of 10,000 images in several formats, and the weight data we used for this experiment was provided from Tensil. Experimental results show that the proposed design process improves the power efficient consumption, hardware utilization, and throughput by 16%, up to 58%, and 15%, respectively.INDEX TERMS FPGA accelerator, CNN accelerator, RT level design techniques, low power techniques, reconfigurable accelerator, CNN-based object detection, low power consumption, high performance, mobile FPGA.

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Section: Convolutional Neural Network(cnn)-based Object Detection App...mentioning

confidence: 99%

A Reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

Kim

Choi

2023

IEEE Access

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“…Chen et al introduced asynchronous behavior for CNN accelerator in 2018 [31]. This accelerator design is made up of processing elements which are aligned as an array of 5 × 5 computation elements with the reconfigurable features for pooling and fully connected layers.…”

Section: State-of-the-art Hardware Architectures For Convolutional Ne...mentioning

confidence: 99%

“…Chen et al [31] Processing elements are arranged according to the kernel size. Reconfigurable features are employed for pooling and fully connected layers also.…”

Section: State-of-the-art Hardware Architectures For Convolutional Ne...mentioning

confidence: 99%

From DNNs to GANs: Review of efficient hardware architectures for deep learning

Bhattacharya¹

2021

Preprint

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In recent times, the trend in very large scale integration (VLSI) industry is multi-dimensional, e.g. reduction of energy consumption, occupancy of less space, precise result, less power dissipation, faster response etc. To meet these needs, the hardware architecture should be reliable and robust to these problems. Recently, neural network and deep learning has been started to impact the present research paradigm significantly which consists of parameters in the order of millions, nonlinear function for activation, convolutional operation for feature extraction, softmax regression for classification, generative adversarial networks, etc. These operations involve huge calculation and memory overhead. Presently available DSP processors are incapable of performing these operations and they most face the problems e.g. memory overhead, performance drop and compromised accuracy. Moreover, if a huge silicon area is powered to accelerate the operation using parallel computation, the IC's will be having significant chance of burning out due to the considerable generation of heat. Hence, novel dark silicon constraint is developed to reduce the heat dissipation without sacrificing the accuracy. Similarly, different algorithms have been adapted to design a DSP processor compatible for fast performance in neural network, activation function, convolutional neural network and generative adversarial network. In this review, we illustrate the recent developments in hardware for accelerating the efficient implementation of deep learning networks with enhanced performance. The techniques investigated in this review are expected to direct future research challenges of hardware optimization for high-performance computations.

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Fault Diagnosis Method for An Aircraft Attitude Control System based on Deep Learning

Luo

Wang

et al. 2021

2021 33rd Chinese Control and Decision Conference (CCDC)

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An asynchronous and reconfigurable CNN accelerator

Cited by 5 publications

References 3 publications

A Reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

A Reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

From DNNs to GANs: Review of efficient hardware architectures for deep learning

Fault Diagnosis Method for An Aircraft Attitude Control System based on Deep Learning

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