2004 IEEE Workshop on Microelectronics and Electron Devices
DOI: 10.1109/wmed.2004.1297347
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An asynchronous GALS interface with applications

Abstract: Abstract-A low-latency asynchronous interface for use in globally-asynchronous locally-synchronous (GALS) integrated circuits is presented. The interface is compact and does not alter the local clocks of the interfaced local clock domains in any way (unlike many existing GALS interfaces). Two applications of the interface to GALS systems are shown. The first is a single-chip shared-memory multiprocessor for generic supercomputing use. The second is an application-specific coprocessor for hardware acceleration … Show more

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Cited by 4 publications
(3 citation statements)
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“…4) [6], [7]. The BML system has been designed so far to be used in the critical real-time systems [9], [13]- [16] and to control them with much higher precision and reliability in comparison to standard solutions. The BML system is designed as a 32bit control unit, where the three-processor MASTER-SLAVE architecture (Fig.…”
Section: Safety Logic Microcontrollermentioning
confidence: 99%
See 1 more Smart Citation
“…4) [6], [7]. The BML system has been designed so far to be used in the critical real-time systems [9], [13]- [16] and to control them with much higher precision and reliability in comparison to standard solutions. The BML system is designed as a 32bit control unit, where the three-processor MASTER-SLAVE architecture (Fig.…”
Section: Safety Logic Microcontrollermentioning
confidence: 99%
“…Therefore, the processors could be provided with additional safety solutions. As the result, three locally separated and independent synchronous computational units (GALS technology -Globally Asynchronous Locally Synchronous [13], [16], [19]) were distinguished inside the BML structure by the processors. Usage of additional function blocks was necessary to ensure the correct functionality of these blocks.…”
Section: Structure and Physical Realization Of Bml Unitmentioning
confidence: 99%
“…Therefore, the processors could be provided with additional safety solutions. As the result, three locally separated and independent synchronous computational units (GALS technology -Globally Asynchronous Locally Synchronous [12]) were distinguished inside the BML structure by the processors. Usage of additional function blocks was necessary to ensure the correct functionality of these blocks.…”
Section: Structure and Physical Realization Of Bml Unitmentioning
confidence: 99%