An attribute grammar approach to high-level automated hardware synthesis

Economakos, George; Παπακωνσταντίνου, Γ.; Tsanakas, Panayiotis

doi:10.1016/0950-5849(95)97293-h

Cited by 14 publications

(14 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Attempting to overcome the inefficiencies of conventional high-level synthesis and propose a unifying formal framework, an AG formalism describing scheduling heuristics was proposed in [4], which operates by decorating the parse tree of a behavioral circuit description with appropriate attributes. Recently [3,6,5], this methodology was realized into the AGENDA integrated design environment that supports top-down implementation of behavioral descriptions using the VHDL hardware description language [2].…”

Section: Introductionmentioning

confidence: 99%

Refinement and Property Checking in High-Level Synthesis Using Attribute Grammars

Economakos

Παπακωνσταντίνου

1999

Lecture Notes in Computer Science

Self Cite

View full text Add to dashboard Cite

Abstract. Recent advances in fabrication technology have pushed the digital designers' perspective towards higher levels of abstraction. Previous work has shown that attribute grammars, used in traditional compiler construction, can also be effectively adopted to describe in a formal and uniform way high-level hardware compilation heuristics, their main advantages being modularity and declarative notation. In this paper, a more abstract form of attribute grammars, relational attribute grammars, are further applied as a framework over which formal hardware verification is performed along with synthesis. The overall hardware design methodology proposed is a novel idea that supports provable correct designs.

show abstract

Section: Introductionmentioning

confidence: 99%

Refinement and Property Checking in High-Level Synthesis Using Attribute Grammars

Economakos

Παπακωνσταντίνου

1999

Lecture Notes in Computer Science

Self Cite

View full text Add to dashboard Cite

show abstract

“…Consequently, traditional programming language methods and tools have been applied for hardware design [6,14,10], their main advantages being design productivity, technology independence and greater potential for design reusability. This paper proposes an interactive synthesis methodology, using Attribute Grammars (AGs) [11] as a formal unified framework over which HLS is performed, following and extending the work presented in [3,4] and [5]. The basic idea is that the parse tree of a behavioral, high-level, language based hardware specification, is used to describe both behavioral and structural details of the design process.…”

Section: ¡ ¾½mentioning

confidence: 99%

Interaction in language based system level design using an advanced compiler generator environment

Poulakis

Economakos²,

Tsanakas³

Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era

View full text Add to dashboard Cite

Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective way to deal with the increasing complexity of digital hardware design. A high-level synthesis tool transforms an abstract algorithmic description into a detailed register transfer level implementation. Even though considerable research has taken place, regarding high-level synthesis, practical implementations are just emerging. This happens due to the fact that designers demand interaction at both the specification and implementation level. This paper describes an efficient implementation of an original idea, for the design of a grammar based interactive design environment, which allows designers supplement high-level synthesis optimizations and set constraints among the operators in the textual algorithmic description to meet their implementation preferences. The suggested methodology raises the feasibility for high level design space exploration by enabling synthesis results to be directly modifiable by the user.

show abstract

“…Attempting to overcome the inefficiencies of high-level synthesis, a unifying formal framework based on AGs was proposed in [6,7,81. These early results have been integrated and extended for the development of the AGENDA 1089-6503/98 $10.00 0 1998 IEEE (Attribute Grammar driven ENvironment for the Design Automation of digital systems) behavioral compiler [9], which performs synthesis by decorating the parse tree of a behavioral circuit description with appropriate attributes (based on the SDP [26] compiler-compiler).…”

Section: Introductionmentioning

confidence: 99%

Exploiting the use of VHDL specifications in the AGENDA high-level synthesis environment

Economakos

Παπακωνσταντίνου²

Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204)

View full text Add to dashboard Cite

Recently, the AGENDA formal framework to perform high-level synthesis using attribute grammars has been presented, its main advantages being modularity and declarative notation in the development of EDA environments. To integrate thisfiameworkwith modern optimization and technology mapping tools, compliance with the corresponding design entry method is needed. This paper gives a brief overview of AGENDA, focuses on diflerent VHDL coding styles that have been adopted to describe the results of highlevel synthesis and attempts comparisons between them. As it has been experimentally tested, the eficiency of thejnal design can be doubled by incorporation of more suitable coding styles. Such results can be proven very valuable in making VHDL an efective tool f o r tomorrow 2 designers.

show abstract

An attribute grammar approach to high-level automated hardware synthesis

Cited by 14 publications

References 28 publications

Refinement and Property Checking in High-Level Synthesis Using Attribute Grammars

Refinement and Property Checking in High-Level Synthesis Using Attribute Grammars

Interaction in language based system level design using an advanced compiler generator environment

Exploiting the use of VHDL specifications in the AGENDA high-level synthesis environment

Contact Info

Product

Resources

About