An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications

Kaul, Meenakshi; Vemuri, Ranga; Govindarajan, Sriram; Ouaiss, Iyad

doi:10.1145/309847.310010

Cited by 52 publications

(28 citation statements)

References 10 publications

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“…In our view, most solutions have one or more of these limitations that distinguish our work from them: (1) compiler optimizations are limited to incremental improvements in the architecture already specified by the programmer, with no real architectural exploration [2,7,12,23], (2) design entry is in a custom highlevel language [7,12,23], (3) the flow is limited to very specific application domain e.g. for image processing or DSP applications [11], (4) the design-space exploration takes a prohibitively long amount of time [12], or (5) soft microprocessors based solutions are created which are not optimized for HPC [2,14]. A flow with high-level, pure software design entry in the functional paradigm, that can apply safe transformations to generate variants automatically, and quickly evaluate them to achieve architectural optimizations, is to the best of our knowledge an entirely novel proposition.…”

Section: Related Workmentioning

confidence: 99%

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Type-Driven Automated Program Transformations and Cost Modelling for Optimising Streaming Programs on FPGAs

Vanderbauwhede

Nabi

Urlea

2018

Int J Parallel Prog

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In this paper we present a novel approach to program optimisation based on compiler-based type-driven program transformations and a fast and accurate cost/performance model for the target architecture. We target streaming programs for the problem domain of scientific computing, such as numerical weather prediction. We present our theoretical framework for type-driven program transformation, our target high-level language and intermediate representation languages and the cost model and demonstrate the effectiveness of our approach by comparison with a commercial toolchain.

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Section: Related Workmentioning

confidence: 99%

“…9. 11 We also compare the effect of varying the array sizes for both cases, which effect the size of internal buffers for stencil data, and hence effect resource utilization.…”

Section: Resource Utilization Comparisonmentioning

confidence: 99%

Type-Driven Automated Program Transformations and Cost Modelling for Optimising Streaming Programs on FPGAs

Vanderbauwhede

Nabi

Urlea

2018

Int J Parallel Prog

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“…A temporal partitioning procedure results in the concept of virtual hardware [31]. The importance of the temporal partitioning (and respectively of the virtual hardware notion) has been demonstrated with large and computationally complex applications [32,33] although the reconfiguration time of the considered FPGAs was relatively high. The mapping procedure in this paper aims in efficiently exploiting the virtual hardware concept.…”

Section: Mapping Onto Fine-grain Reconfigurable Hardwarementioning

confidence: 99%

“…For example, when an application's part does not fit on the FPGA it is discarded by those methods from execution on the FPGA, something that does not occur in the temporal partitioning method. Additionally, it has been shown in [33] that a temporal partitioning based mapping can achieve better execution times compared to a mapping that considers static reconfiguration of the FPGA device.…”

Section: Mapping Onto Fine-grain Reconfigurable Hardwarementioning

confidence: 99%

A method for partitioning applications in hybrid reconfigurable architectures

Galanis

Milidonis

Theodoridis

et al. 2005

Des Autom Embed Syst

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In this paper, we propose a methodology for accelerating application segments by partitioning them between reconfigurable hardware blocks of different granularity. Critical parts are speeded-up on the coarse-grain reconfigurable hardware for meeting the timing requirements of application code mapped on the reconfigurable logic. The reconfigurable processing units are embedded in a generic hybrid system architecture which can model a large number of existing heterogeneous reconfigurable platforms. The fine-grain reconfigurable logic is realized by an FPGA unit, while the coarse-grain reconfigurable hardware by our developed high-performance data-path. The methodology mainly consists of three stages; the analysis, the mapping of the application parts onto fine and coarse-grain reconfigurable hardware, and the partitioning engine. A prototype software framework realizes the partitioning flow. In this work, the methodology is validated using five real-life applications. Analytical partitioning experiments show that the speedup relative to the all-FPGA mapping solution ranges from 1.5 to 4.0, while the specified timing constraints are satisfied for all the applications.

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“…In [10] node is placed the in list as soon as all predecessors have been placed in the list. However, in [6] node is placed in the list as soon as all successors have been placed in the list. The main limitation of this technique is the assignment of tasks, which is based on the control step number (result of ASAP or ALAP scheduling) of each task, rather than the interconnectivity between tasks.…”

Section: Related Workmentioning

confidence: 99%

Synthesis and Time Partitioning for Reconfigurable Systems

Ouni

Mtibaa

Abid

2004

Des Autom Embed Syst

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This paper aims to introduce a time partitioning algorithm which is an important step during the design process for fully reconfigurable systems. This algorithm is used to solve the time partitioning problem. It divides the input task graph model to an optimal number of partitions and puts each task in the appropriate partition so that the latency of the input task graph is optimal. Also a part of this paper is consecrated for implementation of some examples on a fully reconfigurable architecture following our approach.

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An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications

Cited by 52 publications

References 10 publications

Type-Driven Automated Program Transformations and Cost Modelling for Optimising Streaming Programs on FPGAs

Type-Driven Automated Program Transformations and Cost Modelling for Optimising Streaming Programs on FPGAs

A method for partitioning applications in hybrid reconfigurable architectures

Synthesis and Time Partitioning for Reconfigurable Systems

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