An Automatic AW-SOM VHDL IP-core Generator

Abstract

In this paper, the authors present a MATLAB IP generator for hardware accelerators of All-Winner Self-Organizing Maps (AW-SOM). AW-SOM is a modified version of Kohonen's Self Organizing Maps (SOM) algorithm, which is one of the most used Machine Learning algorithms for data clustering, and vector quantization. The architecture of the AW-SOM method is meant for hardware implementations, and its main feature is a processing speed almost independent to the number of neurons since each of them is processed in a parallel way; the parallelization can be easily exploited by hardware custom hardware designs. The IP generator is built-in MATLAB and provides the user with the possibility to design a custom and efficient hardware accelerator. Several settings can be set such as the number of features and the number of neurons. The target language is the VHSIC Hardware Description Language (VHDL). The generated IP cores can be used for the training of the model and a built-in function of the software can also check the clustering performances using its inference capabilities. The accelerators produced by the software have been also characterized in terms of max frequency, hardware resources, and power consumption. The authors performed the hardware implementations on a XILINX Virtex 7 xc7vx690t FPGA.