An autozeroing floating-gate amplifier

Hasler, P.; Minch, B.A.; Diorio, C.

doi:10.1109/82.913189

Cited by 100 publications

(60 citation statements)

References 9 publications

(16 reference statements)

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“…One possible way to reject such offsets would be to use an auto-zeroing amplifier, such as the one proposed by Hasler et al [47], which is capable of rejecting DC offsets in the input signal by using an adaptive floating-gate circuit. For neural amplifiers, another approach to this issue has been the use of differential amplifiers with large coupling capacitors at the inputs [1].…”

Section: ) Thermal Effectsmentioning

confidence: 99%

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces

Datta-Chaudhuri

Smela

Abshire

2016

IEEE Trans. Biomed. Circuits Syst.

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Abstract-CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.Index Terms-Biosensor, heterogeneous integration, lab-on-achip, lab-on-CMOS, microfluidics, system on a chip.

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Section: ) Thermal Effectsmentioning

confidence: 99%

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces

Datta-Chaudhuri

Smela

Abshire

2016

IEEE Trans. Biomed. Circuits Syst.

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“…Floating-Gate (FG) devices and circuits (e.g., [25]) have provided long-term memories for analog computation, enabling very precise programming of values (e.g., 14 bit [26]) for long-term lifetimes (e.g., [27,28]). Memory elements on the order of minutes or longer tend to be more challenging, but possible using adaptive FG techniques from ms to years [29,30], at reasonably low power, including in configurable spaces [31]. Another potential option will be using other long-time-dependent devices, like memristors [32], demonstrated to be integrated with this form of computation.…”

Section: Digital Computationmentioning

confidence: 99%

Starting Framework for Analog Numerical Analysis for Energy-Efficient Computing

Hasler

2017

JLPEA

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Abstract:The focus of this work is to develop a starting framework for analog numerical analysis and related algorithm questions. Digital computation is enabled by a framework developed over the last 80 years. Having an analog framework enables wider capability while giving the designer tools to make reasonable choices. Analog numerical analysis concerns computation on physical structures utilizing the real-valued representations of that physical system. This work starts the conversation of analog numerical analysis, including exploring the relevancy and need for this framework. A complexity framework based on computational strengths and weaknesses builds from addressing analog and digital numerical precision, as well as addresses analog and digital error propagation due to computation. The complimentary analog and digital computational techniques enable wider computational capabilities.

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“…Hasler et al [1] described the Auto-zeroing Floating Gate Amplifier (AFGA) and its use in bandpass filter structures with very low frequency response capability. Minch [2,3] developed circuits and synthesis techniques using Multiple Input Translinear Elements (MITEs) for a variety of signal processing applications.…”

Section: Introductionmentioning

confidence: 99%

Adaptive log domain filters using floating gate transistors

Abshire

Wong

Zhai

et al.

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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We present an adaptive log domain filter with integrated learning rules for model reference estimation. The system is a first order low pass filter based on a log domain topology that incorporates multiple input floating gate transistors to implement on-line learning of gain and time constant. Adaptive dynamical system theory is used to derive robust learning rules for both gain and timeconstant adaptation in a system identification task. The adaptive log domain filters have simulated cutoff frequencies above 100kHz with power consumption of 23 W and show robust adaptation of the estimated gain and time constant as the parameters of the reference filter are changed.

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An autozeroing floating-gate amplifier

Cited by 100 publications

References 9 publications

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces

Starting Framework for Analog Numerical Analysis for Energy-Efficient Computing

Adaptive log domain filters using floating gate transistors

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