An effective capacitance based driver output model for on-chip RLC interconnects

Agarwal, K.; Sylvester, D.; Blaauw, D.

doi:10.1109/dac.2003.1219028

Cited by 11 publications

(3 citation statements)

References 9 publications

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“…Therefore, the conventional timing library format which stores the data for a cell in 2-D lookup tables (LUT) with indices as input transition time (S in ) and effective load capacitance (C ef f ) and outputs as output transition time (S out ) and gate delay is no longer sufficient to model a driver. To this effect, significant work has been done to approximate complex input waveforms by an equivalent waveform [11], to reduce the complex output loads to equivalent load capacitance [4], [9] and to find the delay for MIS using the SIS data [17], [7]. However, none of these methods provide an accurate and comprehensive method for obtaining cell response in the presence of complex input waveforms, output loads and MIS.…”

Section: Introductionmentioning

confidence: 99%

Current source based standard cell model for accurate signal integrity and timing analysis

Goel

Vrudhula

2008

Proceedings of the Conference on Design, Automation and Test in Europe

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The inductance and coupling effects in interconnects and non-linear receiver loads has resulted in complex input signals and output loads for gates in the modern deep submicron CMOS technologies. As a result, the conventional method of timing characterization, which is based on lookup tables with input slew and output load capacitance as indices, is no longer adequate. The focus has now shifted to current source based standard cell models which are based on the fundamental property of transconductance of MOSFETs. In this paper 1 we propose a systematic methodology for obtaining a current based delay model for gates, which can accommodate both single (SIS) and multi-input (MIS) switching signals of arbitrary shape and complex non-linear output loads. We use an analytical model for the gate output current expressed as a function of the node voltages. This results in an average error less than 0.5% with maximum standard deviation of 2.5% in error when compared with SPICE for a large number of standard cells. When compared with SPICE, using the proposed models gives stage delay and output slew with an average error of less than 3% and 2% respectively for arbitrary inputs and output load combinations.

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Section: Introductionmentioning

confidence: 99%

Current source based standard cell model for accurate signal integrity and timing analysis

Goel

Vrudhula

2008

Proceedings of the Conference on Design, Automation and Test in Europe

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“…The timing errors of 0.5V dd -delay and 0.2 − 0.8V dd -slew of LTV models are listed in Table 5. We compare the accuracy of the LTV model with that of the 1-ramp and 2-ramp Thevenin models [3]. The timing statistics of 1-ramp and 2-ramp models are collected from 15 logic stages.…”

Section: Resultsmentioning

confidence: 99%

“…For example, Figure 2(a,b) shows an RC-network and its C eff . Agarwal et al used a two-ramp V th function and two C eff 's, one for each ramp [3]. This approach captures the RC-network loading effect but involves three parameters (two t r 's and one R th ) in the two-segment waveform matching.…”

Section: Previous Workmentioning

confidence: 99%

An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis

Tsai

Marek-Sadowska

Sixth International Symposium on Quality of Electronic Design (ISQED'05)

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This paper presents a two-step, RC-interconnect insensitive linear time-varying (LTV) driver model for gate-level timing calculation. We show how to characterize a driver with the LTV model and how to apply that model in static timing analysis. With the LTV model, the delay error caused by the driver's nonlinearity is reduced significantly because the driver's linear-and saturationregion operations are characterized individually. Because both the linear-and saturation-region models are insensitive to interconnect loads, it is sufficient to use a small number of LTV models for a wide range of possible interconnect loads. Due to the same reason, the LTV model is robust, does not require iterations, and makes timing analysis fast. This method is fast and accurate compared to existing effective capacitance-based methods. Results compared with SPICE simulation demonstrate average 2.5% delay error and 4.4% slew error.

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Cell Delay Analysis Based on Rate-of-Current Change

Nazarian

Pedram

2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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An effective capacitance based driver output model for on-chip RLC interconnects

Cited by 11 publications

References 9 publications

Current source based standard cell model for accurate signal integrity and timing analysis

Current source based standard cell model for accurate signal integrity and timing analysis

An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis

Cell Delay Analysis Based on Rate-of-Current Change

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