An effective DC offset calibration method combined with analog and digital circuits for direct conversion receivers

Wang, Fengjie; Fan, Liyi; Shen, Yupeng; Cheng, Hua; Liu, Jiarui; Wang, Zhiyu; Yu, Faxin

doi:10.1587/elex.16.20190518

Cited by 5 publications

(6 citation statements)

References 32 publications

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“…where R out is the output impedance of the LNA, C 1_para and C 2_para are the parasitic capacitances that are less than 80 fF according to the simulation, and G m is the transconductance of the mixer. With R out being different under different gains of the LNA and the increasing f LO , the equivalent output resistance of the mixer would drop dramatically [30]. Therefore, to confirm the accuracy of the DC offset calibration, R out should be replaced by R replace with a constant resistance, as shown in Figure 10.…”

Section: Dcoc Circuitsmentioning

confidence: 99%

“…The calibration accuracy and range of the DC offset depended on the circuit parameters of the DAC [32]. Therefore, the least significant bit (LSB) of the DAC should be less than the minimum DC offset of the mixers and LPF, while the total current of the DAC should be larger than the maximum DC offset of the mixers and the LPF [30]. According to the equivalent input DC offset voltage of the OPAMP through Monte Carlo simulation [33] and the gain of the mixers and LPF shown in Table 1, the DAC employed in the DCOC circuits is shown in Figure 11.…”

Section: Dcoc Circuitsmentioning

confidence: 99%

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High-Linearity Direct Conversion Receiver with the Transconductance Equalization Technique and DCOC Method

et al. 2021

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To improve the linearity of direct conversion receivers (DCRs), two high-linearity methods for high second-order intercept points (IP2s) and high third-order intercept points (IP3s) are proposed. To improve IP3s, a transconductance equalization technique for a complementary input operational amplifier (OPAMP) is proposed in an active-RC low-pass filter (LPF), while a digital-analog hybrid DC offset calibration (DCOC) method is proposed to improve IP2s. For one thing, the proposed transconductance equalization technique employs a pair of resistors to guarantee high voltage gain for an OPAMP with two-stage Miller topology under a high-input voltage swing to improve linearity with little deterioration of the noise performance. For another, during the DCOC method, the low-noise amplifier is turned off and replaced by an equivalent resistance of the output impedance of the low-noise amplifier to ensure the accuracy and effectiveness of the DCOC method. Fabricated in 40-nm CMOS technology, the receiver with proposed methods can realize a noise figure of 2.6–3.5 dB in the full frequency band, with an OIP3 of 28 dBm, an IM2 more than 70 dBc, and a remaining DC of −53.2 dBm under the total voltage gain of 60 dB.

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Section: Dcoc Circuitsmentioning

confidence: 99%

Section: Dcoc Circuitsmentioning

confidence: 99%

High-Linearity Direct Conversion Receiver with the Transconductance Equalization Technique and DCOC Method

et al. 2021

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“…In traditional direct conversion receiver (DCR) architectures [1], low-noise amplifiers (LNA) are used to provide voltage gain for wanted signal and achieve input matching [2,3,4]. However, receivers with LNA usually suffer from poor linearity [5].…”

Section: Introductionmentioning

confidence: 99%

A 0.1-1.9GHz 65nm CMOS variable-gain mixer-first receiver with DSA and noise-shaping TIA

Song¹,

Wang²,

Liu³

et al. 2023

IEICE Electron. Express

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In this letter, we proposed a highly linear mixer-first receiver with a discrete-step attenuator (DSA) and a noise-shaping TIA. A resistor-reuse technique is devoted to improving linearity and attenuation flatness of the DSA with frequency independance, and a negative impedance chopping method is proposed to reduce the in-band noise of the TIA. Measurement results show that the receiver achieves > 13 dBm IIP3 and in-band noise floor has been depressed by 4 dB, with only consuming 2.82 mW under 1.3 V supply.

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“…Several approaches have been proposed to address this issue, including AC coupling, analog high-pass filtering [11], DC negative feedback loops [12,13], and analog digital DC calibration [30,31,32]. However, these methods tend to occupy a large area of the System on Chip (SoC), and require extended response and stabilization time [14,15,16].…”

Section: Introductionmentioning

confidence: 99%

Ultra-low-power lowpass filter with a novel complementary push-pull DC offset calibration method applied to 5.8GHz Doppler radar

Liu,

Chen,

2023

IEICE Electron. Express

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This paper presents a lowpass filter for 5.8 GHz Doppler radar with an intermediate frequency signal hold function, which significantly reduces system power by interrupt mode operation. Additionally, it proposes a novel complementary push-pull DC offset calibration method to calibrate the DC voltage of the lowpass filter with the common mode voltage. Compared to traditional methods, the proposed scheme effectively stabilize the quiescent operating point of the receiver. The experimental results show that the power consumption of the proposed filter is 0.019 mW, calibrated DC voltage is 1.65 V, and residual DC voltage is less than 1 mV.

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An effective DC offset calibration method combined with analog and digital circuits for direct conversion receivers

Cited by 5 publications

References 32 publications

High-Linearity Direct Conversion Receiver with the Transconductance Equalization Technique and DCOC Method

High-Linearity Direct Conversion Receiver with the Transconductance Equalization Technique and DCOC Method

A 0.1-1.9GHz 65nm CMOS variable-gain mixer-first receiver with DSA and noise-shaping TIA

Ultra-low-power lowpass filter with a novel complementary push-pull DC offset calibration method applied to 5.8GHz Doppler radar

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