An Effective IP Reuse Methodology for Quality System-on-Chip Design

Sarkar, S.; Shinde, Santosh A.; Chandar, S.G.

doi:10.1109/issoc.2005.1595655

Cited by 7 publications

(2 citation statements)

References 5 publications

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“…2 Architecture of SHU-MV10 1) As a stand-alone ASIC design, SHU-MVCAN has the different bus structure from MCU, so it can't hook up to the SHU-MV10 internal bus directly. Options are designing a 'bridge' module to do the interfacing or redesign the bus interface of the IP core [6]. Because of the adequate margin for…”

Section: Shu-mvcanmentioning

confidence: 99%

Reusable Design of CAN Bus Controller IP Core

Lei

2011

AMM

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Intellectual Property (IP) reuse improves System-on-a-Chip (SOC) design productivity, and helps to meet design quality and time-to-marks goals. In this paper, we present an approach to that we successfully adopted in reusing the CAN bus controller IP core. To describe our approach, a MCU design SHU-MV10 is performed. The CAN bus controller IP core is inherited from the stand-alone controller SHU-MVCAN with few modifications, and is used in the design of MCU SHU-MV10 successfully by adding bridge module. This reusable design method is not only cuts down the design time but also ensure the accuracy.

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Section: Shu-mvcanmentioning

confidence: 99%

Reusable Design of CAN Bus Controller IP Core

Lei

2011

AMM

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“…In order to design complex multi-million gate SoCs in today's short time-to-market windows, designers have to rely on the reuse of IP cores to meet the challenges of design productivity gap and achieving the appropriate design quality [1]. Hence, SoC designs are faced with the daunting task of reducing power dissipation because of so many IP cores since power dissipation is quickly becoming a bottleneck for future technologies.…”

Section: Introductionmentioning

confidence: 99%

Adaptive Clock Gating Technique for Low Power IP Core in SoC Design

Chang

Zhang

et al. 2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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Clock gating is a well-known technique to reduce chip dynamic power. This paper analyzes the disadvantages of some recent clock gating techniques and points out that they are difficult in System-on-Chip (SoC) design. Based on the analysis of the Intellectual Property (IP) core model, an adaptive clock gating (ACG) technique which can be easily realized is introduced for the low power IP core design. ACG can automatically enable or disable the IP clock to reduce not only dynamic power but also leakage power with power gating technique. The experimental results on some IP cores in a real SoC show an average of 62.2% dynamic power reduction and 70.9% leakage power reduction without virtually performance impact.

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