An effective on-chip preloading scheme to reduce data access penalty

Last-Touch Correlated Data Streaming

“…Figure 2 shows the cumulative distribution of L1 block dead-times-the number of cycles between a last touch to a block until its eventual eviction. 1 The figure corroborates prior results [12,13,26], showing that over 85% of all cache-block dead-times are longer than the memory access latency. Therefore, prefetch requests issued at last touch can complete before the next access to the same cache index, eliminating the entire off-chip miss latency.…”

“…Temporal correlation distance between two consecutive misses is the distance between the previous occurrence of the same two misses in the sequence of all cache misses. 1 A temporal correlation distance of +1 implies perfect correlation, where the two most recent occurrences of a pair of consecutive misses appeared in exactly the same order; a distance of -1 corresponds to a reversal of the two misses compared to their previous occurrence, as in the sequence {A,B,...,B,A}. Figure 6 (left) shows absolute temporal correlation distances as a cumulative distribution of all cache misses.…”

“…Many proposals are inherently limited in scope, targeting only specific access patterns, such as strided accesses [1,19], pointer dereference [6,8], or accesses to linked data structures [17]. Although frequently accurate for the subset of memory accesses they target, these prefetchers have inherently low coverage overall.…”

Fast, accurate and flexible data locality analysis

“…These techniques may also require the quantification of the different types of cache misses, traditionally noted as compulsory, capacity and conflict misses. For instance, compulsory misses can be avoided through prefetching, both hardware [2] and software [6]. Blocking or tiling is used to avoid capacity misses [3], whereas some examples of techniques to reduce the effect of conflict misses are copying [11] and padding [7].…”

Decoupled access DRAM architecture

“…RAMBUS and synchronous DRAM's utilize a form of on-chip caching and even more aggressive approaches have been proposed 3]. Latency hiding techniques, primarily prefetching 6,7,8], also have been utilized to help solve the problem.…”