An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs

Teslenko, Maxim; Dubrova, Elena

doi:10.1109/date.2005.53

Cited by 4 publications

(4 citation statements)

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“…This is because we can view each edge fault as incrementing weight by one and then it is easy to see that for any vertex t there exists an s − t path if and only if shortest distance between s and t is zero under this reduction. This fact also motivates the study of constructing k-WTSS because k-FTRS has several applications like fault tolerant strongconnectedness [6], dominators [27,6], double dominators [35] etc.…”

Section: Introductionmentioning

confidence: 97%

Near Optimal Sized Weight Tolerant Subgraph for Single Source Shortest Path

Chakraborty,

Das

2017

Preprint

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In this paper we address the problem of computing a sparse subgraph of a weighted directed graph such that the exact distances from a designated source vertex to all other vertices are preserved under bounded weight increment. Finding a small sized subgraph that preserves distances between any pair of vertices is a well studied problem. Since in the real world any network is prone to failures, it is natural to study the fault tolerant version of the above problem. Unfortunately, it turns out that there may not always exist such a sparse subgraph even under single edge failure [Demetrescu et al. '08]. However in real applications it is not always the case that a link (edge) in a network becomes completely faulty. Instead, it can happen that some links become more congested which can easily be captured by increasing weight on the corresponding edges. Thus it makes sense to try to construct a sparse distance preserving subgraph under the above weight increment model where total increase in weight in the whole network (graph) is bounded by some parameter k. To the best of our knowledge this problem has not been studied so far.In this paper we show that given any weighted directed graph with n vertices and a source vertex, one can construct a subgraph that contains at most e • (k − 1)!2 k n many edges such that it preserves distances between the source and all other vertices as long as the total weight increment is bounded by k and we are allowed to have only integer valued (can be negative) weight on each edge and also weight of an edge can only be increased by some positive integer. Next we show a lower bound of c • 2 k n, for some constant c ≥ 5/4, on the size of the subgraph. We also argue that restriction of integer valued weight and integer valued weight increment are actually essential by showing that if we remove any one of these two restrictions we may need to store Ω(n 2 ) edges to preserve distances.

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Section: Introductionmentioning

confidence: 97%

Near Optimal Sized Weight Tolerant Subgraph for Single Source Shortest Path

Chakraborty,

Das

2017

Preprint

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“…In general, a dominator with k nodes is called a k-vertex dominator. For the calculation of dominators we use the algorithms from [18,19,22]. EXAMPLE 3.1.…”

Section: Preliminariesmentioning

confidence: 99%

“…The complexity of finding dominators is O(n k ), where n is the number of graph nodes, and k is the number of nodes in the dominator. The Lengauer-Tarjan algorithm [18] and the algorithms described in [19,22] are used to search for singleand double-vertex dominators, respectively 2 .…”

Section: Core Of the Algorithmmentioning

confidence: 99%

Dominator-based partitioning for delay optimization

Bañeres

Cortadella

Kishinevsky

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

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Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techniques are not always suitable for delay and area logic optimizations. The paper presents an approach that uses a dominator-based partitioning and conventional logic synthesis techniques for delay optimization of large networks. The calculation of dominators is crucial to find topologically ordered clusters suitable for logic restructuring. As a result, a scalable and efficient strategy for delay optimization is proposed and evaluated, showing tangible improvements with respect to existing techniques. A comparison with a standard mincut-based partitioning technique is also presented.

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“…For instance, dominator trees, which are data structures exposing the control dependence in CFGs, were introduced in software compilers to minimize the number of states by removing unnecessary operations without performing reachability analysis in a CFG. Later on, in the context of HLS, dominator trees are exploited to optimize the delay in large Boolean networks [8] or to identify re-converging paths in circuits [96].…”

Section: Control Flow Graphsmentioning

confidence: 99%

Logic synthesis of concurrent control specifications

Ματθαιάκης¹

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The number of transistors per chip increases by 58% per year. At the same time, the designer productivity increases by 21% per year. Thus, an increasing number of design and verification engineers is required to tape-out a chip in the same amount of time. In order to close the design productivity gap the abstraction layer should be raised to boost the design productivity more than the above percentage. For instance, the productivity was increased by 10x in 80s when the state of the art design practice changed from stick diagrams to gate level design. Later on, during the 90s, the productivity increased further by 10x by moving to the RTL level design. Behavioral modeling, lately extended the productivity further by 5x. In behavioral modeling, the control is decoupled from the datapath. It is separately described by HDL structures which correspond to monolithic FSMs, increasing thus the abstraction layer from RTL to FSMs. The underlying EDA tools extract, synthesize and verify monolithic FSMs with algorithms performing at this higher level of abstraction. For instance, state minimization which was originally handled by the engineers themselves, is automatically performed by the EDA tools increasing the quality of results, the design time and the verifiability. Although a monolithic FSM is an adequately powerful formalism to describe sequential circuits, it fails to model concurrency without state explosion. Interacting FSM models have so far lacked the formal rigor for expressing the synchronizing interactions between different FSMs. The event based, PTnet model is able to model both concurrency and choice within the same model, however lacks a polynomial time flow to implementation, as current methods of exposing the event state space require a potentially exponential number of states. In this work, a novel formalism for interacting FSMs is introduced i.e Multiple, Synchronized FSMs (MSFSMs), a compact Interacting FSMs model, potentially implementable using any existing monolithic FSM implementation method. MSFSMs efficiently describe concurrent control systems whilst also acting as an intermediate representation for synthesizing existing specifications described as PTNets with FSMbased flows or for verifying concurrency related properties for systems described as a FSMs with PTNet-based algorithms. PTNet to MSFSMs and MSFSMs to interacting FSMs transformation algorithms are proved in this work to be tractable. Thus, efficient PTNet synthesis and interacting FSMs verification flows are introduced which exploit MSFSMs and which do not exhibit state explosion. Furthermore, novel efficient algorithms introduced at the MSFSM level optimize the control specifications by exploiting the inter-FSM communication. Experimental results indicate that PTNets can indeed be transformed to synthesizable FSMs through transformation to MSFSMs without exhibiting state explosion. A large set of concurrent specifications was transformed to MSFSMs in less than one second each, whereas tools generating the full state space needed days of execution time just to generate specification’s state graph. The logic synthesis framework developed in this work, Expose, approaches the quality of results of logic synthesis tools which generate the exponentially large state space of the specifications, whilst approaching the execution time of the direct-mapping methodologies. Concurrent specifications which could only be implemented through direct mapping, as the execution time for full state space exploration is prohibitive, can now be synthesized using Expose. Our results also show that the MSFSM-based heuristic optimization algorithms drastically and predictably improve the implementation metrics of area and performance as they benefit from the confluence between MSFSMs and state space. By assembling a synthesis flow out of heuristic optimizations, an overall area and performance gain of 80% and 35% respectively was obtained.

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An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs

Cited by 4 publications

References 25 publications

Near Optimal Sized Weight Tolerant Subgraph for Single Source Shortest Path

Near Optimal Sized Weight Tolerant Subgraph for Single Source Shortest Path

Dominator-based partitioning for delay optimization

Logic synthesis of concurrent control specifications

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