An Efficient Algorithm for Online Management of 2D Area of Partially Reconfigurable FPGAs

Chen, Jin; Deng, Qingxu; He, Xiuqiang; Gu, Zonghua

doi:10.1109/date.2007.364579

Cited by 30 publications

(27 citation statements)

References 3 publications

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“…There, the designers improve the system performance and lower the energy consumption by transferring parts of the Operating System kernels to hardware. A similar approach is followed by other authors, e.g., [8,9], where a dedicated hardware resource manager is proposed. The manager makes decisions using heuristic scheduling and placement algorithms.…”

Section: Problem Definition and Related Workmentioning

confidence: 88%

Multithreading on reconfigurable hardware: An architectural approach

Zaykov

Kuzmanov

2012

Microprocessors and Microsystems

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Section: Problem Definition and Related Workmentioning

confidence: 88%

Multithreading on reconfigurable hardware: An architectural approach

Zaykov

Kuzmanov

2012

Microprocessors and Microsystems

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“…In [9], Cui, et al used the same 2D FPGA surface model but with different encoding information. The authors defined maximal key element (MKE) points to utilize the scanning process based on the scan line while looking for the maximum free resource rectangles.…”

Section: Related Workmentioning

confidence: 98%

Searching for complete set of free resource rectangles on FPGA area based on CPTR

Chai

Shen

et al. 2011

J. Shanghai Univ.(Engl. Ed.)

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As a coprocessor, field-programmable gate array (FPGA) is the hardware computing processor accelerating the computing capacity of computers. To efficiently manage the hardware free resources for the placing of tasks on FPGA and take full advantage of the partially reconfigurable units, good utilization of chip resources is an important and necessary work. In this paper, a new method is proposed to find the complete set of maximal free resource rectangles based on the cross point of edge lines of running tasks on FPGA area, and the prove process is provided to make sure the correctness of this method.

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“…Based on this, the time complexity of using bit matrix representation is greater than O(n 2 ). Several schedulers discussed earlier [1,7,12,22] use a bit matrix as their free space data structure or employ a variation of the same size to maintain a data structure, at significant time cost.…”

Section: Bit Matrixmentioning

confidence: 99%

“…Researchers in this area have proposed many algorithms for placement under a variety of assumptions about tasks and the reconfigurable device [2,3,7,11,17,18,21]. The problems can differ based on the type of chip used, as two main models exist for reconfigurable devices: 1D and 2D.…”

Section: Introductionmentioning

confidence: 99%

Maximal strips data structure to represent free space on partially reconfigurable FPGAs

Elbidweihy

Trahan

2009

International Journal of Parallel, Emergent and Distributed Sys

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Partially reconfigurable devices allow the execution of multiple tasks simultaneously on the same chip. To schedule a set of tasks in a small amount of time, the scheduling algorithm will need to represent the free space efficiently. A data structure to represent free space should allow the scheduler to identify free space in which to place a new task and admit efficient updates after placing or removing a task. In this paper, we review some existing data structures and analyse their time complexity. We propose a new structure using maximal horizontal and vertical strips (MHVS) to represent the free space. These strips start and stop at task boundaries. Simulation and time analysis showed that this method has better time complexity than many other free space data structures and at the same time has a very reasonable rejection ratio on real-time tasks compared to other methods.

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An Efficient Algorithm for Online Management of 2D Area of Partially Reconfigurable FPGAs

Cited by 30 publications

References 3 publications

Multithreading on reconfigurable hardware: An architectural approach

Multithreading on reconfigurable hardware: An architectural approach

Searching for complete set of free resource rectangles on FPGA area based on CPTR

Maximal strips data structure to represent free space on partially reconfigurable FPGAs

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