An efficient antilogarithmic converter by using 11-regions error correction scheme

Nandan, Durgesh; Mahajan, Anurag; Kanungo, Jitendra

doi:10.1109/ispcc.2017.8269661

Cited by 10 publications

(11 citation statements)

References 18 publications

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“…From 1962, researchers were trying continuously to propose error-free and hardware efficient approaches to get efficient and accurate antilogarithm [5,10,27,[29][30][31][32][33][34][35]. The entire antilogarithm converter process was adopted broadly in three categories of methods.…”

Section: Systematic Growth Of Literaturementioning

confidence: 99%

“…Kuo [34]. Again in 2019, Durgesh et al [35] have proposed the compact and errorless 16-region error correction scheme for antilogarithm converter which gives better results in terms of hardware overhead as well as accuracy as compared to the reported literature [30][31][32][33][34]. By using ROM, a fast and more accurate conversion is possible.…”

Section: Systematic Growth Of Literaturementioning

confidence: 99%

“…The pictorial representation of logarithm multiplication is shown in Figure 1. Many methods regarding binary to logarithmic conversion and vice versa have been discussed in the last few years [18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35]. Error creates at the time of logarithmic and antilogarithmic conversion [10].…”

Section: Introductionmentioning

confidence: 99%

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An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor

Nandan¹

2020

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Digital Signal Processing (DSP) applications demand error-free and compact hardware architecture of arithmetic operations. A logarithmic operation provides an efficient option in place of binary arithmetic. In this paper, it is suggested that 11-region and 17-region error correction schemes for developing an efficient antilogarithm converter. It is used for developing the most accurate and compact logarithm multiplier which is used in the DSP processor. Implementations of reported and proposed designs are investigate based on accuracy and hardware overhead and it found outperform in comparisons of previously reported designs. The proposed 11-region converter involves 61% less Area Delay Product (ADP) and 49.82% less energy in comparisons of the reported 11-region antilogarithmic converter and 17-region converter involves 48.02% less ADP and 32.53% less energy in comparisons of the reported 14-region antilogarithmic converter. The proposed antilogarithmic converter achieves 1.697% and 1.084% error for 11-region and 17-region designs respectively than of reported designs of 1.876% and 1.351% for 11-region and 17region respectively.

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Section: Systematic Growth Of Literaturementioning

confidence: 99%

Section: Systematic Growth Of Literaturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor

Nandan¹

2020

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“…During 2010 to 2013, the iterative logarithmic approximation was introduced which was based on the correction terms with the high-level of parallelism [43], [44]. In 2016-2018, Durgesh Nandan et al has suggested various changes in logarithm multiplier to make it best in comparisons of existing design [45], [46], [47], [48], [49], [50], [51], [52].…”

Section: E Logarithm Multipliermentioning

confidence: 99%

A Systematic Journal of Multipliers Accuracy and Performance

2019

ijeat

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Low power and efficient architecture of computer arithmetic is demanded of real time Digital signal processing. Out of all arithmetic units, the multiplier is most important and frequently used arithmetic component in literature. As we know that there are many multipliers exist in the literature and everyone has his own proc-corns. But there is a gap in literature, no one gets compared all popular multiplier technique at same platform and discuss their advantages and limitations at one place. This research work outlines the most popular five multiplier techniques (like Wallace, modified, Vedic, Russian Peasant and Logarithm) and compares them, highlights merits, demerit for further improvements. This comprehensive study includes the systematic development, compares the latest design of every multiplier and justified that which one is better over other reported multiplier is also highlighted.

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“…Durgesh Nandan et al have given the Improved Operand Decomposition (IOD) as an approach to minimize the error and had applied to previous logarithmic multiplication approaches [21]. It also suggested various region correction schemes in antilogarithm and logarithm converter to make logarithm multiplication efficient [33][34]. In 2016 and 2018 Durgesh Nandan et.al has try to conclude all literature of logarithm multiplier at one place [35][36].…”

Section: Literature Reviewmentioning

confidence: 99%

An efficient architecture of iterative logarithm multiplier

Nandan¹,

Kanungo²,

Mahajan³

2018

IJET

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Multiplication is one of important arithmetic component for digital signal processing, neural network and image processing. But, it is well known fact that multiplier has most hardware consuming component out of all arithmetic components. Here, it is given a possible solution by using an efficient VLSI architecture of Mitchell's algorithm based Iterative Logarithmic Multiplier (ILM) with modified architecture of Leading One Detector (LOD) and seamless pipelined technique. The proposed work is based on the hardware minimization at the same error cost than of previously reported architectures. We use VHDL to design the existing and proposed Mitchell's algorithm based iterative logarithmic multiplier. Both multipliers design are evaluated with the Synopsys design compiler by using 90 nm CMOS technology and compared the results in terms of Data Arrival Time (DAT), area, power, Area Delay Product (ADP) and energy. The proposed Mitchell's based ILM gives 33.18 %, 39.03 % and 31.62 % less ADP, 25.08 %, 38.08 % and 46.72 % less energy for 8, 16, and 32 bits architecture respectively in comparison of the reported ILM. The importance of LODs and seamless pipeline has been shown in an efficient architecture of Mitchell's based ILM.

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An efficient antilogarithmic converter by using 11-regions error correction scheme

Cited by 10 publications

References 18 publications

An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor

An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor

A Systematic Journal of Multipliers Accuracy and Performance

An efficient architecture of iterative logarithm multiplier

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