An Efficient Approximate Multiplier with Encoded Partial Products and Inexact Counter for Joint Photographic Experts Group Compression

Abstract

Approximate computing is commonly employed in applications where accuracy is not crucial and aims to enhance circuit performance when inaccurate results are not challenging. The multipliers are power‐hungry, and their approximation has been the target of research, especially by using approximate counters. In this study, a low‐power and high‐speed approximate 4 : 2 counter is proposed to add partial product (PP) bits. Also, a new partial product generation (PPG) is introduced by inserting errors in Karnaugh’s map to reduce the circuit complexity. The counter and PPG make a new radix‐4‐based 8 × 8 Booth multiplier, which is synthesized targeting a 32‐nm carbon nanotube field‐effect transistor (CNTFET) technology to determine the hardware characteristics. Looking at the normalized mean error distance (NMED), the multiplier has a 51.33% power–delay product (PDP) saving and acceptable accuracy. Besides, the multiplier which is configured by the counter and PPG accomplishes a 28.31% savings in the PDP × NMED in comparison with other approximate Booth multipliers. The case study of joint photographic experts group (JPEG) compression is performed, and the proposed multiplier outperforms references by higher quality results along with lower power consumption.