An efficient array architecture with data-rings for 3-step hierarchical search block matching algorithm

Abstract

This paper describes an efficient %cells array architecture with data-rings for the 3-step hierarchical search block-matching algorithm. With the efficient data-rings and memory organization, the regular raster-scanned data flow and comparator-tree structure can be used to simplify control scheme and reduce latency, respectively. In addition, we utilise a three-half-search-area scheme to reduce external memory access and interconnection. The results demonstrate that the array architecture with the data-rings gives short latency and low input ports. It also provides a high normalized throughput solution for the 3SHS.