An efficient BER-based reliability method for SRAM-based FPGA

Fouad, Sahraoui; Ghaffari, Fakhreddine; Benkhelifa, Mohamed El Amine; Granado, Bertrand

doi:10.1109/idt.2013.6727129

Cited by 4 publications

(1 citation statement)

References 21 publications

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“…Error Detection and Correction Codes (EDAC) can also be a solution to minimize redundancy overheads. Hardware checkpoint and recovery [5] can also be used to protect computations against faults occurrence and errors propagation with an acceptable time overhead.…”

Section: Introductionmentioning

confidence: 99%

Fast SRAM-FPGA fault injection platform based on dynamic partial reconfiguration

Ghaffari

Fouad

Benkhelifa

et al. 2014

2014 26th International Conference on Microelectronics (ICM)

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SRAM-based FPGAs are very sensitive to harsh conditions, like radiations or ionizations, and need to be hardened to insure correct running. To validate any fault tolerant solution for these SRAM-FPGA, fault injection campaigns must be conducted carefully. In this work, we present a new design flow to perform localized internal fault injection on specific parts of a Design Under Test (DUT). To achieve this, we combine between 1) Partial Dynamic Reconfiguration (PDR) via Internal Configuration Access Port (ICAP) for rapid fault insertion on SRAM; 2) Isolation Design Flow (IDF) to isolate both of placement and routing of Design Under Test into a specific partial region.Moreover, we applied realistic fault distribution laws deduced from ground-based radiation experiments to reflect realistic behavior of FPGA toward radiations. The implemented injection platform using this flow shows the importance of using distribution laws driven approach. Results show that our fault injection experiments are done more than 15 times faster than one of the traditional FPGA based fault injection methods with a speed-up on simulation time up to 8.

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Section: Introductionmentioning

confidence: 99%