1991
DOI: 10.1145/106973.106996
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An efficient cache-based access anomaly detection scheme

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Cited by 5 publications
(7 citation statements)
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“…As mentioned in Section 1, previous works have also investigated hardware and coherence protocol supports for data race detection. Examples include [23,28,32], almost all of which implement the happens-before race detection algorithm by combining with cache coherence protocols in distributed shared memory systems. Most recently, ReEnact [31] employs advanced TLS architecture for race detection and CORD [30] uses scalar logical timestamps to improve the scalability.…”
Section: Related Workmentioning
confidence: 99%
See 1 more Smart Citation
“…As mentioned in Section 1, previous works have also investigated hardware and coherence protocol supports for data race detection. Examples include [23,28,32], almost all of which implement the happens-before race detection algorithm by combining with cache coherence protocols in distributed shared memory systems. Most recently, ReEnact [31] employs advanced TLS architecture for race detection and CORD [30] uses scalar logical timestamps to improve the scalability.…”
Section: Related Workmentioning
confidence: 99%
“…A data race bug is reported when two conflicting memory accesses do not have a strict happens-before relation. Different forms of happens-before algorithm have been implemented in hardware [23,30,31] to overcome the overhead problem (i.e. factor of 10 to 100 slowdowns) in software race detection.…”
Section: Introduction 11 Motivationmentioning
confidence: 99%
“…There are also proposals for race detectors with hardware assists. Some() detect races by tagging the state in the caches as it is being accessed and then piggybacking the tags on cache coherence protocol messages between processors so that they can be compared. The hardware can easily detect an address and an instruction involved in a race on the fly.…”
Section: Discussionmentioning
confidence: 99%
“…Their compression later became the foundation of Netzer's transitivity reduction [15]. Even lower overhead was achieved with a hardware race detector of Min and Choi [14]. Based on cache coherence, this detector timestamps cache blocks with synchronization "era" (with respect to fork/join/barrier synchronizations).…”
Section: The Upper Half Ofmentioning
confidence: 99%