An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

Hatai, Indranil; Chakrabarti, Indrajit; Banerjee, Swapna

doi:10.1109/tcsi.2015.2388838

Cited by 30 publications

(15 citation statements)

References 28 publications

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“…The proposed techniques to reduce the computational complexity can be broadly divided with respect to the optimization goals; reduction in the number of multipliers and reduction in the multiplier complexity [28][29][30][31][32][33][34][35][36][37][38][39][40][41][42]. The contributions of this thesis are towards both research fronts.…”

Section: Motivationmentioning

confidence: 99%

Techniques for Efficient Implementation of FIR and Particle Filtering

Alam

2016

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Finite-length impulse response (FIR) filters occupy a central place many signal processing applications which either alter the shape, frequency or the sampling frequency of the signal. FIR filters are used because of their stability and possibility to have linear-phase but require a high filter order to achieve the same magnitude specifications as compared to infinite impulse response (IIR) filters. Depending on the size of the required transition bandwidth the filter order can range from tens to hundreds to even thousands. Since the implementation of the filters in digital domain requires multipliers and adders, high filter orders translate to a large number of these arithmetic units for its implementation. Research towards reducing the complexity of FIR filters has been going on for decades and the techniques used can be roughly divided into two categories; reduction in the number of multipliers and simplification of the multiplier implementation.One technique to reduce the number of multipliers is to use cascaded subfilters with lower complexity to achieve the desired specification, known as frequency-response masking (FRM). One of the sub-filters is a upsampled model filter whose band edges are an integer multiple, termed as the period L, of the target filter's band edges. Other sub-filters may include complement and masking filters which filter different parts of the spectrum to achieve the desired response. From an implementation point-of-view, time-multiplexing is beneficial because generally the allowable maximum clock frequency supported by the current state-of-the-art semiconductor technology does not correspond to the application bound sample rate. A combination of these two techniques plays a significant role towards efficient implementation of FIR filters. Part of the work presented in this dissertation is architectures for time-multiplexed FRM filters that benefit from the inherent sparsity of the periodic model filters.These time-multiplexed FRM filters not only reduce the number of multipliers but lowers the memory usage. Although the FRM technique requires a higher number delay elements, it results in fewer memories and more energy efficient memory schemes when time-multiplexed. Different memory arrangements and memory access schemes have also been discussed and compared in terms of their efficiency when using both single and dual-port memories. An efficient v vi Abstract pipelining scheme has been proposed which reduces the number of pipelining registers while achieving similar clock frequencies. The single optimal point where the number of multiplications is minimum for non-time-multiplexed FRM filters is shown to become a function of both the period, L and time-multiplexing factor, M . This means that the minimum number of multipliers does not always correspond to the minimum number of multiplications which also increases the flexibility of implementation. These filters are shown to achieve power reduction between 23% and 68% for the considered examples.To simplify the multiplier, alt...

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Section: Motivationmentioning

confidence: 99%

Techniques for Efficient Implementation of FIR and Particle Filtering

Alam

2016

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“…In general, filter coefficients are represented in terms of signed power of two terms (SPTs), which are clubbed and stored in form of sub-expressions, and eliminated on the coefficients set, whenever redundancy is found. Thus, the basic principle involved in CSE is to find redundant expressions on coefficients and eliminate them, which results in efficient filter structure in terms of area, power and speed [9,10,26,36]. This mechanism of CSE for minimizing the adders in implementation of filters is also considered under the multiple constant multiplications (MCM) problems, where the numbers of adders (LO) are minimized to have low complex and efficient hardwired filter [26].…”

Section: Common Sub-expression Elimination Algorithmmentioning

confidence: 99%

“…2. In case of horizontal subexpression elimination (HCSE), matches are found and eliminated horizontally, i.e., the common sub-expression is eliminated within the coefficients (CSWC), while in case of vertical sub-expression elimination (VCSE), the matches are to be found and eliminated vertically, i.e., the common sub-expressions are eliminated across the coefficients (CSAC) [8][9][10]26,36]. A detailed discussion on CSE algorithms can be found in the references [8][9][10]26,36].…”

Section: Common Sub-expression Elimination Algorithmmentioning

confidence: 99%

“…Therefore, the researchers have introduced the concept of CSD, in which each filter coefficient is uniquely represented with minimal number of signed power of two terms (SPTs), and meanwhile the multipliers are completely removed by realizing them in terms of adders and shift network [8,11,25,26]. Adders can be further reduced with the application of common sub-expression elimination (CSE) technique, where sub-expressions, which are common and redundantly present in CSD or binary coefficients, are eliminated [9,10,26,36]. In this realization, the filter coefficients are quantized and represented in terms of SPTs due to which, the performance of filter is degraded; and hence, frequency response characteristics is deteriorated [9,10,26,36].…”

Section: Introductionmentioning

confidence: 99%

“…Adders can be further reduced with the application of common sub-expression elimination (CSE) technique, where sub-expressions, which are common and redundantly present in CSD or binary coefficients, are eliminated [9,10,26,36]. In this realization, the filter coefficients are quantized and represented in terms of SPTs due to which, the performance of filter is degraded; and hence, frequency response characteristics is deteriorated [9,10,26,36]. Therefore, it is needed to design an optimal filter bank that satisfies the distinct design specifications along with efficiently realized structures, when it is hardwired.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An Efficient Method for Designing Multiplier-Less Non-uniform Filter Bank Based on Hybrid Method Using CSE Technique

Sharma

Kumar

Singh

2016

Circuits Syst Signal Process

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This paper presents an efficient method for optimal design of multiplierless non-uniform tree-structured filter banks using hybrid evolutionary algorithm. Phenomenal reduction in number of adders is achieved by applying common subexpression elimination (CSE) on canonic signed digits (CSD) and binary represented filter coefficients. The proposed methodology utilizes the proficiencies of particle swarm optimization and artificial bee colony algorithms to achieve magnitude response of a prototype filter for non-uniform filter bank (NUFB) of 0.7071 at quadrature frequency. Single optimization technique is employed for designing the computationally efficient, continuous and quantized coefficients of a prototype filter for NUFB. A comprehensive study on CSE technique such as vertical, horizontal and mixed CSE has been also made for designing NUFB. The simulation results reflect that the proposed method shows better performance in terms of adder gain and reconstruction error. The hybrid method yields 33 % of adder gain with CSD technique and 55 % adder gain in case of CSE technique. B I. Sharma

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