An Efficient Decoder Scheme for Double Binary Circular Turbo Codes

Zhan, Cheng; Arslan, Tughrul; Erdogan, A.T.; MacDougall, S.

doi:10.1109/icassp.2006.1660947

Cited by 21 publications

(25 citation statements)

References 5 publications

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“…The initial forward and backward state metrics of each frame can be attained by two distinct methods for the WiMAX-based standard and LTE-based standard. The method used in WiMAX-based standard is the circular encoding [21], which ensure the ending trellis state equals the initial trellis state. Thus, the initial values of the forward state metrics a k 0 (s) and backward …”

Section: Circular Parallel Map Decodingmentioning

confidence: 99%

Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems

Lin¹,

Chen²,

Chang

et al. 2013

J Sign Process Syst

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For high-mobility 4G applications of LTE-A and WiMAX-2 systems, this paper presents a dual-standard turbo decoder design with the following three techniques. 1) Circular parallel decoding reduces decoding latency and improves throughput rate. 2) Collision-free vectorizable dual-standard parallel interleaver enhances hardware utilization of the interleaving address generator. 3) One-bank extrinsic buffer design with bit-level extrinsic information exchange reduces size of the extrinsic buffer compared with the two-bank extrinsic buffer design. Furthermore, a multistandard turbo decoder chip is fabricated in a core area of 3.38 mm 2 by 90 nm CMOS process. This chip is maximally measured at 152 MHz with 186.1 Mbps for LTE-A standard and 179.3 Mbps for WiMAX-2 standard.

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Section: Circular Parallel Map Decodingmentioning

confidence: 99%

Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems

Lin¹,

Chen²,

Chang

et al. 2013

J Sign Process Syst

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show abstract

“…To determine the initial values, two methods are generally preferred. The first one is to pre-compute several trellis stages to get reliable initial values [6]. Another way is to use the metric values of the prior iteration [5] [6].…”

Section: Max-log-map Algorithmmentioning

confidence: 99%

“…The first one is to pre-compute several trellis stages to get reliable initial values [6]. Another way is to use the metric values of the prior iteration [5] [6]. It has been reported that using the information of the prior iteration shows better performance and lower computational complexity than the pre-computing method [6].…”

Section: Max-log-map Algorithmmentioning

confidence: 99%

Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding

Kim

Park

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-This paper presents an energy-efficient turbo decoder based on border metric encoding, which is especially suitable for non-binary circular turbo codes. In the proposed method, the size of the branch memory is reduced to half and the dummy calculation is removed at the cost of a small-sized memory that holds encoded border metrics. Due to the small size and infrequent access to the border memory, power consumption for soft-input soft-output (SISO) decoding is reduced by 26.0%. Based on the proposed SISO decoder and the dedicated hardware interleaver, a double-binary tail-biting turbo decoder is designed for WiMAX standard using a 0.18 µm CMOS process and it can support 12.14Mbps at operating frequency of 100MHz.

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“…As shown in Figure 6, four branch transitions are associated with each α/β state update. The decoding algorithm for double binary codes is inherently based on the Radix-4 algorithm (Zhan, 2006), hence the same Radix-4 α, β and L(φ) function units as used in the binary codes can be applied to the double binary codes in a straightforward manner. The only different parts are the branch metrics γ ij calculations and the tail-biting trellis termination scheme.…”

Section: Radix-4 Decoding Of Double Binary Turbo Codesmentioning

confidence: 99%

“…For double binary codes, the main difference with ordinary binary codes is the trellis termination scheme and the symbol-wise decoding scheme (Zhan, 2006). The double binary trellis is closed as a circle with the start state equal to the end state.…”

Section: Radix-4 Decoding Of Double Binary Turbo Codesmentioning

confidence: 99%

Configurable and Scalable Turbo Decoder for 4G Wireless Receivers

Sun

Cavallaro

Zhu

et al.

Advances in Wireless Technologies and Telecommunication

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The increasing requirements of high data rates and quality of service (QoS) in fourth-generation (4G) wireless communication require the implementation of practical capacity approaching codes. In this chapter, the application of Turbo coding schemes that have recently been adopted in the IEEE 802.16e WiMax standard and 3GPP Long Term Evolution (LTE) standard are reviewed. In order to process several 4G wireless standards with a common hardware module, a reconfigurable and scalable Turbo decoder architecture is presented. A parallel Turbo decoding scheme with scalable parallelism tailored to the target throughput is applied to support high data rates in 4G applications. High-level decoding parallelism is achieved by employing contention-free interleavers. A multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. A new on-line address generation technique is introduced to support multiple Turbo interleaving patterns, which avoids the interleaver address memory that is typically necessary in the traditional designs. Design trade-offs in terms of area and power efficiency are analyzed for different parallelism and clock frequency goals.

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An Efficient Decoder Scheme for Double Binary Circular Turbo Codes

Cited by 21 publications

References 5 publications

Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems

Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems

Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding

Configurable and Scalable Turbo Decoder for 4G Wireless Receivers

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