An efficient design for reversible Wallace unsigned multiplier

PourAliAkbar, Ehsan; Mosleh, Mohammad

doi:10.1016/j.tcs.2018.06.007

Cited by 29 publications

(6 citation statements)

References 20 publications

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“…Booth multiplier consumed more voltage (4.2V) and more cycle duration (50ns) to write the data in output terminal. E. Pouraliakbar and M. Mosleh [18] proposed an efficient design for reversible Wallace unsigned multiplier. In this paper, two 4x4 reversible unsigned multipliers were used to design WTM.…”

Section: Literature Reviewmentioning

confidence: 99%

VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

Monica¹,

Anuradha²,

Syed³

et al. 2021

IJIES

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Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).

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Section: Literature Reviewmentioning

confidence: 99%

VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

Monica¹,

Anuradha²,

Syed³

et al. 2021

IJIES

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“…Parallel multipliers are the preferred solution if a high-speed architecture is required. Furthermore, multipliers can be both signed and unsigned 3 .…”

Section: Introductionmentioning

confidence: 99%

A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

Kalaiselvi,

Sabeenian

2023

Sci Rep

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A technique for efficiently multiplying two signed numbers using limited area and high speed is presented in this paper. This work uses both the Booth and Vedic multiplication sutra methodologies to enhance the speed and reduction in the area by using two VLSI architectures of radix encoding techniques—Radix-4 and Radix-8—with the Vedic multiplier. The functionality of the proposed methods is tested using an Artix-7 Field Programmable Gate Array (FPGA-XC7A100T-CSG324) in Xilinx Vivado 2019.1 and ASIC 45 nm technology. Two methods of Booth encoding using Vedic multiplier (Urdhva-Tiryakbhyam sutra) were used to develop, and examine the benefits of rapid computational multiplier. The results of the proposed multiplier for Booth-Vedic-Radix-4 encoding (BVR-4) decrease area by 89% and improve Area-Delay Product (ADP) by 72% for a 16-bit multiplier when subjected to other existing multipliers. The Booth-Vedic-Radix-8 (BVR-8) method shows that there will be an 89% reduction in area and an improvement in ADP by 72% for the 16-bit multiplier. The performance is evaluated regarding area occupancy (i.e., LUTs number) and propagation delay (output time). In terms of resource utilization, the proposed BVR-4 and BVR-8 multipliers outperform all the current designs with a marginal effect on speed and area for narrower bit-width ranges.

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“…The quantum cost of a reversible (

1 \times 1)

gate (known as NOT gate) and (

2 \times 2

) gates (e.g., the Controlled V + , Controlled V, and Controlled NOT (CNOT)), and lastly, the integrated 2‐qubit gates is one, as shown in Figure 1A–E. Furthermore,

(V \times V) = (V^{+} \times V^{+}) = NOT

and (

V \times V^{+}) = (V^{+} \times V) = I

, where I represents a unitary matrix 15–19 …”

Section: Introductionmentioning

confidence: 99%

“…, where I represents a unitary matrix. [15][16][17][18][19] This paper is significant for the following contributions:…”

Section: Introductionmentioning

confidence: 99%

A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits

Noorallahzadeh

Mosleh

Ahmadpour

et al. 2023

Int J Numerical Modelling

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Reversible logic is used increasingly to design digital circuits with lower power consumption. The parity preserving (PP) property contributes to detect permanent and transient faults in reversible circuits by comparing the input and output parity. Multiplication is also considered one of the primary operations in both digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, Vedic mathematics, as a set of techniques sutras, has become popular and is extensively used to solve mathematical problems more efficiently and faster. This work proposes three PP reversible blocks, N1, N2, and N3, which are used to develop a novel effective 2‐bit PP reversible Vedic multiplier and 4‐bit ripples carry adders (RCAs). Moreover, 2‐bit Vedic multiplier and RCA are used to develop the 4‐bit PP reversible Vedic multiplier. The proposed designs outperform the most relevant state‐of‐the‐art structures in terms of garbage output (GO), constant input (CI), gate count (GC), and quantum cost (QC). Average savings of 22.37%, 35.44%, 35.44%, and 34.76%, and 17.76%, 26.60%, 24.52%, and 27.27% respectively, are observed for two‐bit and four‐bit PP reversible Vedic multipliers in terms of QC, GO, CI and GC as compared to previous works.

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An efficient design for reversible Wallace unsigned multiplier

Cited by 29 publications

References 20 publications

VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits

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