Res. Journ. Scie. and Technol.
 2018
DOI: 10.5958/2349-2988.2018.00015.3
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An Efficient Design of 8-bit High Speed Parallel Prefix Adder

Garima Thakur1,
Harsh Sohal2,
Shruti Jain3
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Cited by 7 publications
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A Novel ASIC-Based Variable Latency Speculative Parallel Prefix Adder for Image Processing Application

Thakur
1
,
Sohal
2
,
Jain
3
2021
Circuits Syst Signal Process
19
0
3
0
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A Novel ASIC-Based Variable Latency Speculative Parallel Prefix Adder for Image Processing Application

Thakur
1
,
Sohal
2
,
Jain
3
2021
Circuits Syst Signal Process
19
0
3
0
View full textAdd to dashboardCite

Power–Area-Optimized Approximate Multiplier Design for Image Fusion

Thakur,
Sohal,
Jain
2023
Circuits Syst Signal Process
0
0
0
0
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Design and Analysis of High-Speed Parallel Prefix Adder for Digital Circuit Design Applications

Thakur
1
,
Sohal
2
,
Jain
3
2020
2020 International Conference on Computational Performance Evaluation (ComPE)
13
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