An Efficient Design of Latches for Multi-Clock Multi-Microcontroller System on Chip for Bus Synchronization

Abstract

Speed is a very interesting feature of present time systems either it is electronic or mechanical. From a long time system designers are trying to speed up the system. There are many constraints for the designers as only speed of the system is not required cost, power, size and complexity should not increase up to a certain limit. Now in case of microprocessor/microcontroller speed is the main consideration. No one wants the lower speed microprocessor/microcontroller. Any embedded system speed is dependent on the speed of the processor. Early time processor designers were followed a concept of increasing the number of data lines. In the processor design first four bit microprocessor was developed after that eight, sixteen, thirty two and so on. But soon this concept was saturated as the number of lines increases up to a large extent. The complexity and power dissipation increases due to the increase in the capacitance by these lines. In the same way the concept of pipelining was also saturated after a certain design complexity level. So designers move to a new architecture that is the multi-core architecture. In multi core architecture similar microcontrollers are connected in parallel. These microcontrollers are connected to a common shared bus. So the speed of the multi-microcontroller architecture depends on speed of the interconnection network. This interconnection network is nothing but network-on-chip (NoC). So there is a need of synchronization of the buses of microcontrollers to common shared bus by means of arbitration technique. To synchronize the buses we need tri state buffers/latches. In this paper, we have explored several critical aspects in the design of the latches. Latches are required for the bus synchronization of multi-microcontroller system on programmable chip (MMSoPC).