An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability

Zheng, Feijun; Cheng, Kwang-Ting; Yan, Xiaolang; Moondanos, John; Hanna, Ziyad

doi:10.1109/ats.2007.4388027

Cited by 5 publications

(8 citation statements)

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“…In addition a fast fault pair filter is inserted between the two phases to improve the efficiency of the OPG procedure. In summary the proposed method has the following advantages: 1) the two-phase-based DPG is more efficient, requiring less CPU time, 2) the modified circuit in the proposed method needs only two copies of the original circuit compared to three copes in [1] and four copies in [8], resulting in less ATPG complexity, and (3) only combinational ATPG for stuck-at faults is involved compared to the sequential ATPG requirement in [9].…”

Section: Proposed Diagnostic Pattern Generationmentioning

confidence: 99%

“…[n [1 ]- [9] some diagnostic test generation procedures are proposed to generate more patterns to distinguish most fault pairs. [n particular, the work in [[] [8] [9] are specifically aimed to deal with transition faults that are the main targets of AC diagnosis in industry. In [1], a three-phase diagnostic pattern generation method for transition faults is developed that requires only a combinational stuck-at fault ATPG tool.…”

Section: Introductionmentioning

confidence: 99%

“…All possible conditions for distinguishing two transition faults are considered based on a 3-copy model of the original circuit. [n [8], a Boolean Satisfiability (SAT) based method is proposed and a faulty circuit model composed of a two-timeframe circuit and a 4-to-1 multiplexer is employed to model a transition fault. A modified circuit is then built by connecting two faulty circuit models to 978-1-4799-3282-5/14/$31.00 mOl4 IEEE model a pair of transition faults.…”

Section: Introductionmentioning

confidence: 99%

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Efficient pattern generation for transition-fault diagnosis using combinational circuit model

Wang

Lee

2014

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

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An efficient diagnosis procedure to distinguish non-equivalent transition faults and identify equivalent transition faults is proposed. This procedure consists of three main methods. The Fault Inactivation Method (FIM) generates diagnosis patterns to distinguish fault pairs by inactivating one fault and detecting the other for each fault pair, the Fault Pair Filter Method (FPF) quickly identifies a large portion of equivalent-fault pairs after FIM, and the Fault Propagation Method (FPM) generates diagnosis patterns for the remaining distinguishable fault pairs and identifies equivalent-fault pairs by initializing both faults in each pair simultaneously and creating distinguishable faulty responses. Experimental results show that only 6 out of more than 7.48*10 8 fault pairs in ISCAS89 benchmark circuits cannot be handled by this method, i.e., a diagnosis resolution of higher than 99.999999% is achieved.

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Section: Proposed Diagnostic Pattern Generationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Efficient pattern generation for transition-fault diagnosis using combinational circuit model

Wang

Lee

2014

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

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“…This heuristic does not guarantee to find counterexamples that strengthen the diagnosis. Diagnostic Test Pattern Generation (DTPG) [11] calculates traces to distinguish given faults, but requires a specific fault model like stuck-at faults, and is therefore not modelfree. For debugging the fault model is typically unknown.…”

Section: Introductionmentioning

confidence: 99%

Using QBF to increase accuracy of SAT-based debugging

Sülflow

Fey

Drechsler

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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Abstract. The burden of debugging significantly slows down the design process of complex systems. Only limited tool support is available and a typical experience is that fixing one problem only leads to finding the next one. Here, we propose an approach that integrates formal verification with diagnosis. The approach is based on Quantified Boolean Formulas (QBF) and ensures, that counterexamples of high quality are returned. Moreover, the diagnosis algorithm only returns fault candidates that can fix all counterexamples. By this, the total number of fault candidates decreases and less iterations between verification and debugging are required.

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“…The second step is Diagnostic Trace Generation (DTG). Similar to diagnostic test patterns [27] [28], diagnostic traces distinguish the behavior of fault candidates [15]. DTG works on sequential circuits and does not require a precise fault model.…”

Section: Generalized Automated Debugging Proceduresmentioning

confidence: 99%

Automated debugging from pre-silicon to post-silicon

Dehbashi¹,

Fey²

2012

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Abstract-Due to the increasing design size and complexity of modern Integrated Circuits (IC) and the decreasing time-tomarket, debugging is one of the major bottlenecks in the IC development cycle. This paper presents a generalized approach to automate debugging which can be used in different scenarios from design debugging to post-silicon debugging. The approach is based on model-based diagnosis. Diagnostic traces are proposed as an enhancement reducing debugging time and increasing diagnosis accuracy. The experimental results show the effectiveness of the approach in post-silicon debugging.

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An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability

Cited by 5 publications

References 0 publications

Efficient pattern generation for transition-fault diagnosis using combinational circuit model

Efficient pattern generation for transition-fault diagnosis using combinational circuit model

Using QBF to increase accuracy of SAT-based debugging

Automated debugging from pre-silicon to post-silicon

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