An efficient energy and thermal-aware mapping for regular network-on-chip

Abstract

Chip temperature and energy consumption become one of the most critical design issues with technology scaling to nanometre-scale, especially for NoC systems with large number of cores and shrunken core size. To balance the temperature and energy consumption on NoC-based multi-cores system, this paper proposes an efficient NoC mapping approach in which the hyper-heuristic algorithm based on genetic operators (HAGO) is the core of this approach. Compared to simulated annealing algorithm and genetic algorithm, HAGO demonstrates a faster convergence speed and excellent stability. Experimental results show that our proposed mapping approach can make a better balance between energy consumption and temperature, which reduces the peak temperature from 365.2 K to 352 K and only increases the energy consumption by 1.12%.

Thermal placement on PCB of components including 3D ICs

“…Thermalaware floorplanning methods for VLSI have been proposed [3,4,5,6,7,8,9]. Thermal-aware 3D network-on-chip (NoC) designs have been proposed [10,11]. Related to the thermal placement of 3D ICs, thermal through-silicon-via (TSV) optimization [12,13,14,15,16] and thermal floor plans [17,18,19,20,21,22,23,24,25,26] have been presented.…”