An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set $\{2n+1,2n,2n-1\}$

Novel RNS-to-binary converters for the three-moduli set {2m − 1, 2m, 2m + 1}

“…The hardware requirement and conversion time for the various reverse converters described in [5,18,19,21] for the moduli set M1 along with the proposed reverse converters have been presented in table 1. Note that FA, HA, AND and w:1 MUX stand for a full adder, half adder, twoinput AND gate and w:1 multiplexer, respectively.…”

“…In the converter D4 for M1 proposed by Wang et al [19] based on new CRT II technique, we need one 2k 9 k multiplier and one k 9 k multiplier, a few adders and a few comparators. The recent converter D5 for M1 due to Gbolagade et al [21] is based on the modification of CRT. It realizes modulo m 1 reduction using several MUXs and comparators and it needs one 2k 9 k multiplier and one k 9 k multiplier.…”

“…The proposed converters D6-D10 as well as design D5 [21] were implemented using Cadence (Version 14.20), Compiler: RC 14.25 and synthesized using the Cadence Encounter tool using 180-nm technology. The post place and route results of area, conversion time and power dissipation for all these designs for DRs of 8, 16, 24, 32, 48 and 64 bits are presented in table 5.…”

“…Premkumar [5] suggested the three-moduli set M1 {2m -1, 2m, 2m ? 1} and several reverse converters for M1 have been reported in the literature [5,[18][19][20][21]. The first reverse converter for M1 is presented in [5] using CRT.…”

“…Reverse converters for this moduli set using New CRT II [22] also have been investigated [19]. More recently, improved reverse converters for this moduli set using CRT have been presented [20,21]. However, these converters can be considered to be similar to a Mixed Radix Conversion (MRC)-type design.…”