An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs

Zhu, Chuhong; Huang, Kejie; Yang, Shuyuan; Zhu, Ziqi; Zhang, Hejia; Shen, Haibin

doi:10.1109/tvlsi.2020.3002779

Cited by 93 publications

(68 citation statements)

References 30 publications

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“…Compared to the work in [26], this study uses the same frequency of 100 MHz, but our work achieved a performance improvement of 1.38× and energy efficiency by 1.63×. Compared to the accelerator in [36], this design uses only 471 DSPs and operates at a 100 MHz frequency, much less than those values in [36]. This work achieves a 2.64× improvement in sparsity, although its energy efficiency is lower than that in [36].…”

Section: B Experiments Results Of Fpga Implementationmentioning

confidence: 86%

“…Compared to the accelerator in [36], this design uses only 471 DSPs and operates at a 100 MHz frequency, much less than those values in [36]. This work achieves a 2.64× improvement in sparsity, although its energy efficiency is lower than that in [36]. Althought, the performance of the accelerator in [37] is higher when using 2 × the frequency and 2× the DSP resources, this work achieves higher energy efficiency.…”

Section: B Experiments Results Of Fpga Implementationmentioning

confidence: 97%

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An Energy-Efficient Implementation of Group Pruned CNNs on FPGA

Pang

2020

IEEE Access

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In recent years, convolutional neural network (CNN)-based artificial intelligence algorithms have been widely applied to object recognition and image classification tasks. However, the high performance of convolutional neural networks comes at the cost of high-intensity computing and enormous numbers of parameters, which pose substantial challenges to terminal implementations. An end-to-end FPGA-based accelerator is proposed in this work that efficiently processes fine-grained pruned CNNs. A group pruning algorithm with group sparse regularization (GSR) is introduced to solve internal buffer misalignments and load imbalances of the accelerator after fine-grained pruning. A mathematical model of accelerator access and transmission is established to explore the optimal design scale and calculation mode. The accelerator is optimized by designing sparse processing elements and by scheduling the on-and off-chip buffers. The proposed approach reduces the computation of a state-of-the-art large-scale CNN, VGG16, by 86.9% with an accuracy loss on CIFAR-10 of only 0.48%. The accelerator achieves 188.41 GOPS at 100 MHz and consumes 8.15 W when implemented on a Xilinx VC707, making it more energy-efficient than previous approaches.

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Section: B Experiments Results Of Fpga Implementationmentioning

confidence: 86%

Section: B Experiments Results Of Fpga Implementationmentioning

confidence: 97%

An Energy-Efficient Implementation of Group Pruned CNNs on FPGA

Pang

2020

IEEE Access

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“…However, they only focused on the zeros in activation maps, while the parameters in filters' weights were not taken into considerations. On the other hand, there are several works [10] and [18] that have considered zeros in weights, but they are typically combined with zero compression methods to support sparse networks. In general, these methods require additional data buffers which would cause increased power consumption when the number of zeros is not so large or the target network is dense, which motivates us to develop a power-efficient accelerator design to support both dense and sparse networks.…”

Section: Preliminariesmentioning

confidence: 99%

Power-Efficient Deep Convolutional Neural Network Design Through Zero-Gating PEs and Partial-Sum Reuse Centric Dataflow

Lin

Yanagisawa

et al. 2021

IEEE Access

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Convolution neural networks (CNNs) have shown great success in many areas such as object detection and pattern recognition at the cost of extreme high computation complexity and significant external memory access, which makes state-of-the-art deep CNNs difficult to be implemented on resource-constrained portable/wearable devices with limited capacity of battery. To address this design challenge, a power-efficient CNN design through zero-gating processing elements (PEs) and partial-sum reuse centric dataflow is proposed in this paper. Unlike the existing works which either only consider the zeros in activation maps or use off-chip training process for on-chip computation reduction, a zero-gating PE design is proposed to avoid unnecessary on-chip computation by taking advantages of the large number of zeros in both the filter's weights of pre-trained models and the activation maps. Furthermore, a partial-sum reuse centric dataflow is also proposed for off-chip DRAM access reduction. The evaluation results show that the overall power consumption of PE arrays with our proposal can be reduced by 37% and 14% at the cost of 8% and 1% area overhead when compared to the baseline PE design and the existing only-activation-gated design (i.e. that in Eyeriss), respectively. Moreover, the proposed method can achieve 35% and 47% DRAM access reduction with the corresponding 14% and 49% energy savings for AlexNet and VGG-16 when compared to that in Eyeriss.

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“…Similar to Argus, SparseNN [17] and Cambricon-x [18] take advantage of skipping zeros in CNN weights. Beside mentioned, there are many other highquality architectures in terms of performance, like Eyeriss v2 [12], ENVISION [18], Thinker [19], UNPU [20], Snowflake [22], Caffeine [23], CoNNa [24], and architectures in [25]- [27].…”

Section: Introductionmentioning

confidence: 99%

Argus CNN Accelerator Based on Kernel Clustering and Resource-Aware Pruning

Rakanovic

Vranjkovic

Struharik

2021

ELEKTRON ELEKTROTECH

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Paper proposes a two-step Convolutional Neural Network (CNN) pruning algorithm and resource-efficient Field-programmable gate array (FPGA) CNN accelerator named “Argus”. The proposed CNN pruning algorithm first combines similar kernels into clusters, which are then pruned using the same regular pruning pattern. The pruning algorithm is carefully tailored for FPGAs, considering their resource characteristics. Regular sparsity results in high Multiply-accumulate (MAC) efficiency, reducing the amount of logic required to balance workloads among different MAC units. As a result, the Argus accelerator requires about 170 Look-up tables (LUTs) per Digital Signal Processor (DSP) block. This number is close to the average LUT/DPS ratio for various FPGA families, enabling balanced resource utilization when implementing Argus. Benchmarks conducted using Xilinx Zynq Ultrascale + Multi-Processor System-on-Chip (MPSoC) indicate that Argus is achieving up to 25 times higher frames per second than NullHop, 2 and 2.5 times higher than NEURAghe and Snowflake, respectively, and 2 times higher than NVDLA. Argus shows comparable performance to MIT’s Eyeriss v2 and Caffeine, requiring up to 3 times less memory bandwidth and utilizing 4 times fewer DSP blocks, respectively. Besides the absolute performance, Argus has at least 1.3 and 2 times better GOP/s/DSP and GOP/s/Block-RAM (BRAM) ratios, while being competitive in terms of GOP/s/LUT, compared to some of the state-of-the-art solutions.

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An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs

Cited by 93 publications

References 30 publications

An Energy-Efficient Implementation of Group Pruned CNNs on FPGA

An Energy-Efficient Implementation of Group Pruned CNNs on FPGA

Power-Efficient Deep Convolutional Neural Network Design Through Zero-Gating PEs and Partial-Sum Reuse Centric Dataflow

Argus CNN Accelerator Based on Kernel Clustering and Resource-Aware Pruning

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