An efficient hardware based MAC design in digital filters with complex numbers

Basiri, M. Mohamed Asan; Sk, Noor Mahammad

doi:10.1109/spin.2014.6777000

Cited by 8 publications

(11 citation statements)

References 10 publications

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“…The critical path of [8] includes only one log 2 2n bit CLA. Therefore, critical path delay of [8] is less than proposed design. The total cycles (N cycles ) (12) required for a particular design in Table 4 depends on the number of pipeline stages (N p ), number of operations required (N o ), and a number of possible operations in parallel (N pr ).…”

Section: Design Modelling Implementation and Resultsmentioning

confidence: 99%

“…In [6, 7], carry save array multiplier (Braun) is used in the critical path that includes n carry save stages. In [8], multiple pipeline stages are used in carry save stages and the 2 n bit recursive doubling‐based CLA is the part of the critical path that includes

\log_{2} n

stages. In [6–8], accumulation is done along with present multiplication and hence the separate accumulator is not required.…”

Section: Design Modelling Implementation and Resultsmentioning

confidence: 99%

“…The array multiplier-based MACs [6][7][8] are used in modern applications, where only one MAC operation is performed. In the recent trends, reconfigurable digital systems play a major role, where the same hardware is used to perform multiple operations (vectored or non-vectored).…”

Section: Related Workmentioning

confidence: 99%

“…1c are not used during 16 × 16 bit MAC mode. In most of the non-vector MAC designs [6][7][8][18][19][20][21], the flexibility to perform multiple MAC operations is absent. For example, second, third, and fourth quarters of Figs.…”

Section: Related Workmentioning

confidence: 99%

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Quadruple throughput fixed point quarter precision multiply accumulate circuit design

Basiri

Mohammad

2017

IET Computers & Digital Techniques

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This study proposes an efficient very large scale integration (VLSI) architecture for quadruple throughput fixed point multiply accumulate circuit (MAC). The proposed n × n bits MAC is used to perform one n × n bits or two n × (n/2) bits or four (n/2) × (n/2) bits MAC operations in parallel. The objective of the proposed MAC is to improve throughput of the existing MAC designs. The proposed and existing designs are implemented by 45 nm CMOS TSMC library and the results show that the proposed architecture achieves better improvement in throughput than existing designs. For example, the proposed 32 × 32 bits MAC architecture achieves 60.4% of improvement in throughput over existing array multiplier-based double throughput MAC.

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Section: Design Modelling Implementation and Resultsmentioning

confidence: 99%

\log_{2} n

stages. In [6–8], accumulation is done along with present multiplication and hence the separate accumulator is not required.…”

Section: Design Modelling Implementation and Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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Quadruple throughput fixed point quarter precision multiply accumulate circuit design

Basiri

Mohammad

2017

IET Computers & Digital Techniques

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“…Mohamed Asan Basiri M et.al [1] have proposed a MAC Design in Digital Filters with Complex Numbers. They designed a novel fixed point complex number multiply accumulate circuit, which is used in real time digital signal processing applications.…”

Section: Related Workmentioning

confidence: 99%

Review of High Speed 32-bit Single Precision Floating Point Complex Multiplier using Vedic Mathematics

Kewate¹,

Indurkar²,

Hinganikar³

2016

International Journal of Innovative Research in Electrical, Ele

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Multipliers are essential component of digital signal processing as they are used for determining the speed of Digital Signal Processor (DSP). The floating point complex multiplication is one of the basic functions used in digital signal processing application, microprocessors and FIR filters. Floating point format is a standard format used almost in all processing elements. Delay and power are main parameters used to determine the speed of multiplier. Conventional multipliers require more delay and hence consume more power for the multiplication. The Vedic mathematics technique is widely used because of its fast computational ability. This paper presents a review of 32bit single precision floating point complex multiplier using Vedic mathematics and proposes a design for high speed 32 bit single precision floating point complex multiplier using Vedic mathematic.

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Asynchronous Hardware Design for Floating Point Multiply-Accumulate Circuit

Basiri

2019

Communications in Computer and Information Science

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An efficient hardware based MAC design in digital filters with complex numbers

Cited by 8 publications

References 10 publications

Quadruple throughput fixed point quarter precision multiply accumulate circuit design

Quadruple throughput fixed point quarter precision multiply accumulate circuit design

Review of High Speed 32-bit Single Precision Floating Point Complex Multiplier using Vedic Mathematics

Asynchronous Hardware Design for Floating Point Multiply-Accumulate Circuit

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