Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems 2011
DOI: 10.1145/2038698.2038707
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An efficient heuristic for instruction scheduling on clustered vliw processors

Abstract: Clustering is a well-known technique for improving the scalability of classical VLIW processors. A clustered VLIW processor consists of multiple clusters, each of which has its own register file and functional units. This paper presents a novel phase coupled priority-based heuristic for scheduling a set of instructions in a basic block on a clustered VLIW processor. Our heuristic converts the instruction scheduling problem into the problem of scheduling a set of instructions with a common deadline. The priorit… Show more

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Cited by 11 publications
(8 citation statements)
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“…CAeSaR runs just before register allocation, as shown in Figure 6. To evaluate CAeSaR's performance, we measure the total size (in cycles) of the schedules generated by the compiler under CAeSaR and compare it against two state-of-the-art clustering algorithms (UAS [28] and CS [37]). …”
Section: Methodsmentioning
confidence: 99%
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“…CAeSaR runs just before register allocation, as shown in Figure 6. To evaluate CAeSaR's performance, we measure the total size (in cycles) of the schedules generated by the compiler under CAeSaR and compare it against two state-of-the-art clustering algorithms (UAS [28] and CS [37]). …”
Section: Methodsmentioning
confidence: 99%
“…CAeSaR can work with various clustering heuristics, but the implementation shown makes use of the Start-Cycle heuristic [9,17] which, according to [31], is the best for clustered architectures with low inter-cluster communication delays (like the 1-cycle delay we consider). Other heuristics such as the Completion-Cycle [9] or the Critical-Successor [37] could also be used instead. The main body of the CAeSaR algorithm is listed in Algorithm 1.…”
Section: High Level Overviewmentioning
confidence: 99%
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