An Efficient Heuristic for Peak Capture Power Minimization During Scan-Based Test

Trinadh, A. Satya; Potluri, Seetal; Babu, Ch. Sobhan; Kamakoti, V.

doi:10.1166/jolpe.2013.1255

Cited by 2 publications

(3 citation statements)

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“…Gate level techniques include clock gating Sankaralingam and Touba 2002], scan cell output gating [et al 2008], and low power scan chain synthesis [Gerstendorfer and Wunderlich 1999;Girard et al 1999;Parimi and Sun 2004;Potluri et al 2013]. System level techniques include low power test pattern generation [et al 2007], power aware test scheduling [Yao et al 2011], test pattern ordering [Girard et al 1998;Dabholkar et al 1998;Trinadh et al 2013] and don't care filling Wu et al 2011;Trinadh et al 2014]. All of these test pattern ordering and don't care filling techniques for Launch-Off-Shift (LOS) scheme Wu et al 2011;Trinadh et al 2014] are heuristics without a performance guarantee.…”

Section: Related Workmentioning

confidence: 99%

“…Column 1 shows the benchmark name and column 2 shows minimum peak input toggles obtained among all aforementioned don't care filling methods, under test cube ordering given by the T etraM ax T M tool. In the technique proposed in [Trinadh et al 2013], only the impact of test cube ordering is considered, while in [Wu et al 2011] only the impact -fill b01 3 4 4 3 3 3 b02 4 4 4 4 4 4 b03 15 19 18 15 8 7 b04 45 52 47 43 25 24 b05 21 24 21 23 15 14 b06 5 4 5 5 5 4 b07 27 33 38 25 15 14 b08 16 20 18 15 8 7 b09 20 19 and MSTSP-ordering + DP-fill, the former performs the best benchmarks whose test sets are dominated by don't cares (> ≈ 75% don't cares), and the latter performs the best otherwise. So, I-ordering + DP-fill is good for circuits whose test sets are dominated for don't cares and MSTSP-ordering + DP-fill is good circuits whose test sets are not dominated by don't cares.…”

Section: Maximum Scatter Traveling Salesman Path Problem (Mstspp)mentioning

confidence: 99%

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Optimal Don’t Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing

Trinadh

Potluri

Babu

et al. 2017

ACM Trans. Des. Autom. Electron. Syst.

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Due to the increase in manufacturing/environmental uncertainties in the nanometer regime, testing digital chips under different operating conditions becomes mandatory. Traditionally, stuck-at tests were applied at slow speed to detect structural defects and transition fault tests were applied at-speed to detect delay defects. Recently, it was shown that certain cell-internal defects can only be detected using at-speed stuck-at testing. Stuck-at test patterns are power hungry, thereby causing excessive voltage droop on the power grid, delays the test response and finally leading to false delay failures on the tester. This motivates the need for peak power minimization during at-speed stuck-at testing. In this paper, we use input toggle minimization as a means to minimize circuit's power dissipation during at-speed stuck-at testing under the CSP-scan DFT scheme. For circuits whose test sets are dominated by don't cares, this paper maps the problem of optimal X-filling for peak input toggle minimization to a variant of interval coloring problem and proposes a dynamic programming (DP) algorithm (DP-fill) for the same along with a theoretical proof for its optimality. For circuits whose test sets are not dominated by don't cares, we propose a max scatter Hamiltonian path algorithm, which ensures that the ordering is done such that the don't cares are evenly distributed in the final ordering of test cubes, thereby leading to better input toggle savings than DP-fill. The proposed algorithms, when experimented on ITC99 benchmarks, produced peak power savings of up to 48% over the best known algorithms in literature. We have also pruned the solutions thus obtained, using Greedy and Simulated Annealing strategies with iterative 1-bit neighborhood, to validate our idea of optimal input toggle minimization as an effective technique for minimizing peak power dissipation during at-speed stuck-at testing.

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Section: Related Workmentioning

confidence: 99%

Section: Maximum Scatter Traveling Salesman Path Problem (Mstspp)mentioning

confidence: 99%

Optimal Don’t Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing

Trinadh

Potluri

Babu

et al. 2017

ACM Trans. Des. Autom. Electron. Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…Gate level techniques include clock gating [10], [15], scan cell output gating [12], and low power scan chain synthesis [1], [5], [8]- [10]. System level techniques include low power test pattern generation [16], power aware test scheduling [17], test pattern ordering [13], [14], [20] and X-filling [19], [21], [22]. All of these X-filling techniques for Launch-On-Shift (LOS) scheme [19], [21], [22] are heuristics without a performance guarantee.…”

Section: Related Workmentioning

confidence: 99%

Dp-Fill: A Dynamic Programming Approach to X-Filling for Minimizing Peak Test Power in Scan Tests

Trinadh

Babu

Singh

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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At-speed testing is crucial to catch small delay defects that occur during the manufacture of high performance digital chips. Launch-Off-Capture (LOC) and Launch-Off-Shift (LOS) are two prevalently used schemes for this purpose. LOS scheme achieves higher fault coverage while consuming lesser test time over LOC scheme, but dissipates higher power during the capture phase of the at-speed test. Excessive IR-drop during capture phase on the power grid causes false delay failures leading to significant yield reduction that is unwarranted. As reported in literature, an intelligent filling of don't care bits (X-filling) in test cubes has yielded significant power reduction. Given that the tests output by automatic test pattern generation (ATPG) tools for big circuits have large number of don't care bits, the X-filling technique is very effective for them. Assuming that the design for testability (DFT) scheme preserves the state of the combinational logic between capture phases of successive patterns, this paper maps the problem of optimal X-filling for peak power minimization during LOS scheme to a variant of interval coloring problem and proposes a dynamic programming (DP) algorithm for the same along with a theoretical proof for its optimality. To the best of our knowledge, this is the first ever reported X-filling algorithm that is optimal. The proposed algorithm when experimented on ITC99 benchmarks produced peak power savings of up to 34% over the best known low power X-filling algorithm for LOS testing. Interestingly, it is observed that the power savings increase with the size of the circuit.

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An Efficient Heuristic for Peak Capture Power Minimization During Scan-Based Test

Cited by 2 publications

References 0 publications

Optimal Don’t Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing

Optimal Don’t Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing

Dp-Fill: A Dynamic Programming Approach to X-Filling for Minimizing Peak Test Power in Scan Tests

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