An Efficient Implementation of AES on 8-Bit AVR-Based Sensor Nodes

Kim, YoungBeom; Seo, Seog Chung

doi:10.1007/978-3-030-65299-9_21

Cited by 7 publications

(10 citation statements)

References 6 publications

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“…architecture Until now, CTR mode optimization has been conducted only on 8-bit AVR, Intel Core i2, and Intel Core i7 [4][5][6][7][8]. However, there are many types of IoT platforms.…”

Section: First Parallel Implementation Of Ctr Mode On Embedded Devices Using Armv8mentioning

confidence: 99%

“…HIGHT was designed in a feistel structure and is a lightweight block cipher that encrypts 64-bit block through a 128-bit secret key. The HIGHT' round function is composed of lightweight arithmetic such as modular addition by 2 8 , rotate (F 0 and F 1 functions), and XOR operations in 8-bit units, so it is very suitable for low-end processors with limited resources. Furthermore, HIGHT was designated as an ISO/IEC 18033-3 [15] in 2010.…”

Section: Instructions Operands Description Cyclesmentioning

confidence: 99%

“…Furthermore, HIGHT was designated as an ISO/IEC 18033-3 [15] in 2010. In the key schedule process of HIGHT, the delta value is updated through Linear-Feedback Shift Register (LFSR), and subkeys are generated by computing the modular addition by 2 8 on one byte of the master key and the delta value. In LFSR, the connected polynomial uses x 7 + x 3 + 1, so the delta has a period of 127.…”

Section: Instructions Operands Description Cyclesmentioning

confidence: 99%

“…In the encryption process of HIGHT, it is composed of an initial and final conversion performed at the beginning and end of encryption, and round functions. The initial and final transformations operate byte-wise XOR operation and modular addition by 2 8 . The round function performs F 0 , F 1 function, XOR, and modular addition by 2 8 operations.…”

Section: Instructions Operands Description Cyclesmentioning

confidence: 99%

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Efficient Parallel Implementation of CTR Mode of ARX-Based Block Ciphers on ARMv8 Microcontrollers

Song

Seo

2021

Applied Sciences

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With the advancement of 5G mobile telecommunication, various IoT (Internet of Things) devices communicate massive amounts of data by being connected to wireless networks. Since this wireless communication is vulnerable to hackers via data leakage during communication, the transmitted data should be encrypted through block ciphers to protect the data during communication. In addition, in order to encrypt the massive amounts of data securely, it is essential to apply one of secure mode of operation. Among them, CTR (CounTeR) mode is the most widely used in industrial applications. However, these IoT devices have limited resources of computing and memory compared to typical computers, so that it is challenging to process cryptographic algorithms that have computation-intensive tasks in IoT devices at high speed. Thus, it is required that cryptographic algorithms are optimized in IoT devices. In other words, optimizing cryptographic operations on these IoT devices is not only basic but also an essential effort in order to build secure IoT-based service systems. For efficient encryption on IoT devices, even though several ARX (Add-Rotate-XOR)-based ciphers have been proposed, it still necessary to improve the performance of encryption for smooth and secure IoT services. In this article, we propose the first parallel implementations of CTR mode of ARX-based ciphers: LEA (Lightweight Encryption Algorithm), HIGHT (high security and light weight), and revised CHAM on the ARMv8 platform, a popular microcontroller in various IoT applications. For the parallel implementation, we propose an efficient data parallelism technique and register scheduling, which maximizes the usage of vector registers. Through proposed techniques, we process the maximum amount of encryption simultaneously by utilizing all vector registers. Namely, in the case of HIGHT and revised CHAM-64/128 (resp. LEA, revised CHAM-128/128, and CHAM-128/256), we can execute 48 (resp. 24) encryptions simultaneously. In addition, we optimize the process of CTR mode by pre-computing and using the intermediate value of some initial rounds by utilizing the property that the nonce part of CTR mode input is fixed during encryptions. Through the pre-computation table, CTR mode is optimized up until round 4 in LEA, round 5 in HIGHT, and round 7 in revised CHAM. With the proposed parallel processing technique, our software provides 3.09%, 5.26%, and 9.52% of improved performance in LEA, HIGHT, and revised CHAM-64/128, respectively, compared to the existing parallel works in ARM-based MCU. Furthermore, with the proposed CTR mode optimization technique, our software provides the most improved performance with 8.76%, 8.62%, and 15.87% in LEA-CTR, HIGHT-CTR, and revised CHAM-CTR, respectively. This work is the fastest implementation of CTR mode on ARMv8 architecture to the best of our knowledge.

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“…architecture Until now, CTR mode optimization has been conducted only on 8-bit AVR, Intel Core i2, and Intel Core i7 [4][5][6][7][8]. However, there are many types of IoT platforms.…”

Section: First Parallel Implementation Of Ctr Mode On Embedded Devices Using Armv8mentioning

confidence: 99%

Section: Instructions Operands Description Cyclesmentioning

confidence: 99%

Section: Instructions Operands Description Cyclesmentioning

confidence: 99%

Section: Instructions Operands Description Cyclesmentioning

confidence: 99%

See 2 more Smart Citations

Efficient Parallel Implementation of CTR Mode of ARX-Based Block Ciphers on ARMv8 Microcontrollers

Song

Seo

2021

Applied Sciences

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“…In Table 4, we summarize some commands and related information for the commands that are used in this paper. We focus on ATmega128 since it is widely used in for sensor nodes [28]. The target device has the following resources: 128 KB of flash memory, 4 KB SRAM, and 4 KB EEPROM.…”

Section: Overview Of 8-bit Avr Mcusmentioning

confidence: 99%

Chaining Optimization Methodology: A New SHA-3 Implementation on Low-End Microcontrollers

2021

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Since the Keccak algorithm was selected by the US National Institute of Standards and Technology (NIST) as the standard SHA-3 hash algorithm for replacing the currently used SHA-2 algorithm in 2015, various optimization methods have been studied in parallel and hardware environments. However, in a software environment, the SHA-3 algorithm is much slower than the existing SHA-2 family; therefore, the use of the SHA-3 algorithm is low in a limited environment using embedded devices such as a Wireless Sensor Networks (WSN) enviornment. In this article, we propose a software optimization method that can be used generally to break through the speed limit of SHA-3. We combine the θ, π, and ρ processes into one, reducing memory access to the internal state more efficiently than conventional software methods. In addition, we present a new SHA-3 implementation for the proposed method in the most constrained environment, the 8-bit AVR microcontroller. This new implementation method, which we call the chaining optimization methodology, implicitly performs the π process of the f-function while minimizing memory access to the internal state of SHA-3. Through this, it achieves up to 26.1% performance improvement compared to the previous implementation in an AVR microcontroller and reduces the performance gap with the SHA-2 family to the maximum. Finally, we apply our SHA-3 implementation in Hash_Deterministic Random Bit Generator (Hash_DRBG), one of the upper algorithms of a hash function, to prove the applicability of our chaining optimization methodology on 8-bit AVR MCUs.

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